Abstract: An electronic package structure and a chip thereof are provided. The electronic package structure includes a supporting element, a chip, an internal bonding wire, and a plurality of external bonding wires. The supporting element has a chip arrangement portion. The chip has a first surface and a second surface opposite to the first surface. The chip is arranged on the chip arrangement portion with the second surface facing toward the supporting element. The chip includes a first common pad and an individual core pad that are disposed on the first surface. The internal bonding wire is connected between the first common pad and the individual core pad. The external bonding wires are connected between the chip and the supporting element, in which a first external bonding wire of the external bonding wires and the internal bonding wire are jointly connected to the first common pad.

Abstract: An integrated circuit includes a load circuit and an electrostatic discharge (ESD) circuit. The load circuit includes a first and a second I/O terminal. The ESD circuit is coupled to the first and the second I/O terminal. The ESD circuit includes a first protection circuit configured to conduct a first ESD current from the first to the second I/O terminal. The first protection circuit includes a first, a second, a third doped region, and a well. The first doped region is coupled to the first I/O terminal, and has a first conductive type. The well is coupled to the first doped region, and has a second conductive type different from the first conductive type. The second doped region is coupled to the well, and has the first conductive type. The third doped region couples the second doped region to the second I/O terminal, and has the second conductive type.

Abstract: A diode, which is implemented in a semiconductor structure, includes a substrate, and first, second, third and fourth conductors. The substrate contains first and second doped regions. The first and second doped regions are used respectively as a first electrode and a second electrode of the diode. The first and third conductors are in a first conductor layer of the semiconductor structure and are connected to the first and second doped regions, respectively. The second and fourth conductors are in a second conductor layer of the semiconductor structure and are connected to the first and third conductors, respectively. In a side view of the semiconductor structure, an overlapping area between the first conductor and the third conductor is larger than an overlapping between of the second conductor and the fourth conductor.

Abstract: An integrated circuit includes a load circuit and an electrostatic discharge (ESD) circuit. The load circuit includes a first and a second I/O terminal. The ESD circuit is coupled to the first and the second I/O terminal. The ESD circuit includes a first protection circuit configured to conduct a first ESD current from the first to the second I/O terminal. The first protection circuit includes a first, a second, a third doped region, and a well. The first doped region is coupled to the first I/O terminal, and has a first conductive type. The well is coupled to the first doped region, and has a second conductive type different from the first conductive type. The second doped region is coupled to the well, and has the first conductive type. The third doped region couples the second doped region to the second I/O terminal, and has the second conductive type.

Abstract: This disclosure provides an ESD protection circuit coupled to a first and a second terminals of a differential-pair circuit. The ESD protection circuit includes: an ESD sensing unit coupled to the first and the second terminals and sensing electrical changes at the first and the second terminals to generate a first trigger signal; and a first discharging unit coupled to the ESD sensing unit and turning on a first discharging path according to the first trigger signal.

Abstract: An ESD protection circuit includes: a first current path switch arranged in a parallel connection with a first circuit and turned off when a first node voltage is at a logic low level; a first node for providing the first node voltage; a resister element coupled between a first power terminal and the first node; a MOS capacitor coupled between the first node and a first fixed-voltage terminal; a second current path switch arranged in a parallel connection with a second circuit and controlled by a second node voltage; a switch control circuit for providing the second node voltage; and a node voltage control circuit for controlling the first node voltage according to the second node voltage to ensure the first current path switch is turned off when the first power terminal supplies power to the first circuit while the second power terminal supplies power to the second circuit.

Abstract: An Ethernet communication circuit includes: an Ethernet cable connector for communicating data with other devices through an Ethernet cable; an Ethernet transformer coupled with the Ethernet cable connector and arranged to operably process signals transmitted from the Ethernet cable connector; an Ethernet physical layer circuit coupled with the Ethernet transformer and arranged to operably conduct physical layer operations on the signals transmitted from the Ethernet transformer; and a plurality of coupling capacitors respectively arranged between a portion of signal pins of the Ethernet physical layer circuit and the Ethernet transformer.

Abstract: An ESD protection circuit includes: a first current path switch arranged in a parallel connection with a first circuit and turned off when a first node voltage is at a logic high level; a first node for providing the first node voltage; a resister element coupled between a first power terminal and the first node; a MOS capacitor coupled between the first node and a first fixed-voltage terminal; a second current path switch arranged in a parallel connection with a second circuit and controlled by a second node voltage; a switch control circuit for providing the second node voltage; and a node voltage control circuit for controlling the first node voltage according to the second node voltage to ensure the first current path switch is turned off when the first power terminal supplies power to the first circuit while the second power terminal supplies power to the second circuit.

Abstract: An electrostatic discharge protection element is provided, which leads out the electrostatic discharge current between an internal circuit and an input/output terminal in the event of electrostatic discharge. The electrostatic discharge protection element includes an I/O pad, conductor, and a gap structure. The I/O pad is connected between the I/O terminal and the internal circuit, and the conductor is connected to a ground terminal. The gap structure is disposed between the I/O pad and the conductor, which is configured to establish a path from the I/O pad to the conductor connected to the ground terminal for conducting the electrostatic discharge current.

Abstract: The present invention discloses a current-mirror-based electrostatic discharge (ESD) clamping circuit comprising: a first power terminal; a second power terminal; a current-mirror-based ESD detector; a driver; and an ESD clamping element. The current-mirror-based ESD detector includes: a resistor coupled between the first power terminal and a detection-output-terminal; a semiconductor capacitor coupled between the detection-output-terminal and an ESD triggered current mirror; and the ESD triggered current mirror operable to electrically connect the semiconductor capacitor and/or the detection-output-terminal with the second power terminal according to the level of a driving signal under an ESD operation. The driver is operable to generate the driving signal according to the voltages of the detection-output-terminal and the first and second power terminals.

Abstract: An ESD protection circuit includes: a first current path switch arranged in a parallel connection with a first circuit and turned off when a first node voltage is at a logic high level; a first node for providing the first node voltage; a resister element coupled between a first power terminal and the first node; a MOS capacitor coupled between the first node and a first fixed-voltage terminal; a second current path switch arranged in a parallel connection with a second circuit and controlled by a second node voltage; a switch control circuit for providing the second node voltage; and a node voltage control circuit for controlling the first node voltage according to the second node voltage to ensure the first current path switch is turned off when the first power terminal supplies power to the first circuit while the second power terminal supplies power to the second circuit.

Abstract: An ESD protection circuit includes: a first current path switch arranged in a parallel connection with a first circuit and turned off when a first node voltage is at a logic low level; a first node for providing the first node voltage; a resister element coupled between a first power terminal and the first node; a MOS capacitor coupled between the first node and a first fixed-voltage terminal; a second current path switch arranged in a parallel connection with a second circuit and controlled by a second node voltage; a switch control circuit for providing the second node voltage; and a node voltage control circuit for controlling the first node voltage according to the second node voltage to ensure the first current path switch is turned off when the first power terminal supplies power to the first circuit while the second power terminal supplies power to the second circuit.

Abstract: This disclosure provides an ESD protection circuit coupled to a first and a second terminals of a differential-pair circuit. The ESD protection circuit includes: an ESD sensing unit coupled to the first and the second terminals and sensing electrical changes at the first and the second terminals to generate a first trigger signal; and a first discharging unit coupled to the ESD sensing unit and turning on a first discharging path according to the first trigger signal.

Abstract: A regulator includes a driving circuit, an amplifying circuit and an overvoltage protection circuit. The driving circuit is configured to receive an input voltage and provide an output voltage through an output terminal. The amplifying circuit is configured to control the driving circuit according to the output voltage. The overvoltage protection circuit is configured to conduct a first current from the output terminal of the overprotection circuit to a ground terminal. When the overvoltage protection circuit detects that a voltage level of a node coupled to the driving circuit is increased, the overvoltage protection circuit conducts a second current from the output terminal of the overprotection circuit to the ground terminal to lower the output voltage, in which the second current is larger than the first current.

Abstract: A regulator includes a driving circuit, an amplifying circuit and an overvoltage protection circuit. The driving circuit is configured to receive an input voltage and provide an output voltage through an output terminal. The amplifying circuit is configured to control the driving circuit according to the output voltage. The overvoltage protection circuit is configured to conduct a first current from the output terminal of the overprotection circuit to a ground terminal. When the overvoltage protection circuit detects that a voltage level of a node coupled to the driving circuit is increased, the overvoltage protection circuit conducts a second current from the output terminal of the overprotection circuit to the ground terminal to lower the output voltage, in which the second current is larger than the first current.

Abstract: The disclosure provides an ESD protection circuit. The ESD protection circuit comprises: a clamping unit, a driving unit, a resistance unit, a switch unit, and a capacitance unit. The clamping device is coupled between a first power source and a second power source. The driving unit is coupled between the clamping device and a reference node. The resistance unit is coupled between the first power source and the reference node. The switch unit is coupled to the driving unit via the reference node. The capacitance unit is coupled between the switch unit and the second power source. Under a normal operation condition, the driving unit controls the switch unit to be in an un-conducting status. Under an ESD condition, the driving unit controls the switch unit to be in a conducting status.

Abstract: An ESD protection circuit includes a plurality of resistors, at least a capacitor, a driving circuit and an ESD clamping device, wherein a first node of each resistor is connected to a first supply voltage, and a second node of each of at least a portion of the resistors is selectively connected to an input node via a corresponding switch respectively, and a first node of the capacitor is connected to a second supply voltage, and a second node of the capacitor is connected to the input node; the driving circuit is arranged to generate a driving signal according to a voltage on the input node; and the ESD clamping device is coupled to the driving circuit, and connected between the first supply voltage and the second supple voltage, and the ESD clamping device is arranged to selectively bypass an ESD current according to the driving signal.

Abstract: An electrostatic discharge protection element is provided, which leads out the electrostatic discharge current between an internal circuit and an input/output terminal in the event of electrostatic discharge. The electrostatic discharge protection element includes an I/O pad, conductor, and a gap structure. The I/O pad is connected between the I/O terminal and the internal circuit, and the conductor is connected to a ground terminal. The gap structure is disposed between the I/O pad and the conductor, which is configured to establish a path from the I/O pad to the conductor connected to the ground terminal for conducting the electrostatic discharge current.

Abstract: The present invention discloses a current-mirror-based electrostatic discharge (ESD) clamping circuit comprising: a first power terminal; a second power terminal; a current-mirror-based ESD detector; a driver; and an ESD clamping element. The current-mirror-based ESD detector includes: a resistor coupled between the first power terminal and a detection-output-terminal; a semiconductor capacitor coupled between the detection-output-terminal and an ESD triggered current mirror; and the ESD triggered current mirror operable to electrically connect the semiconductor capacitor and/or the detection-output-terminal with the second power terminal according to the level of a driving signal under an ESD operation. The driver is operable to generate the driving signal according to the voltages of the detection-output-terminal and the first and second power terminals.

Abstract: An electronic device includes a core circuit and multiple pad units. The core circuit includes multiple core MOS and the multiple pad units are respectively electrically connected to the core circuit. Each pad unit includes at least one pad MOS. A core gate in each core MOS and a pad gate in each pad MOS extend along the same direction or extend parallel with each other.