Patents by Inventor Cheng-En Lee

Cheng-En Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11264204
    Abstract: The present disclosure relates to a method includes generating ions with an ion source of an ion implantation apparatus based on an ion implantation recipe. The method includes accelerating the generated ions based on an ion energy setting in the ion implantation recipe and determining an energy spectrum of the accelerated ions. The method also includes analyzing a relationship between the determined energy spectrum and the ion energy setting. The method further includes adjusting at least one parameter of a final energy magnet (FEM) of the ion implantation apparatus based on the analyzed relationship.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsiung Lin, Cheng-En Lee, Chia-Lin Ou, Hsuan-Pang Liu, Yao-Jen Yeh
  • Publication number: 20220059320
    Abstract: An ion implantation system comprising: a sample platform; an ion gun; an electrostatic linear accelerator; a direct current (DC) final energy magnet (FEM); and a processor. The processor is programmed to control: a wafer acceptance test instrument, a DC recipe calculator, a DC real energy calculator, and a tool energy shift verifier. The wafer acceptance test instrument is configured to apply a wafer acceptance test (WAT) recipe to a test sample on the sample platform. The DC recipe calculator is configured to calculate a recipe for the DC FEM. The DC real energy calculator is configured to calculate a real energy of the DC FEM. The tool energy shift verifier is configured to verify a tool energy shift of the DC FEM. The ion implantation system is configured to tune the DC FEM based on the verified tool energy shift, and obtain a peak magnetic field of the DC FEM.
    Type: Application
    Filed: November 1, 2021
    Publication date: February 24, 2022
    Inventors: Yi-Hsiung LIN, Yao-Jen YEH, Chia-Lin OU, Cheng-En LEE, Hsuan-Pang LIU
  • Publication number: 20220033560
    Abstract: A method for preparing a heat-moisture-resistant polyurethane elastomer includes (A) providing a polyol and an aliphatic diisocyanate to react in the presence of a suitable catalyst under a heating environment, thereby forming a urethane prepolymer with an reactive isocyanate terminal group; (B) providing a hydrophobic diol with a hydroxyl group and/or a castor oil-based triol as a chain extender; and (C) performing an addition reaction of the urethane prepolymer and the chain extender under an appropriate heating environment to generate the heat-moisture-resistant polyurethane elastomer that can be used for a long time in a warm and humid environment.
    Type: Application
    Filed: July 31, 2020
    Publication date: February 3, 2022
    Inventors: CHANG-LUN LEE, BEI-HUW SHEN, CHENG-EN LEE, BIING-SHANN YU, MING-HUANG LIN, CHIN-LUNG CHIANG
  • Patent number: 11164722
    Abstract: A method of tuning an ion implantation apparatus is disclosed. The method includes operations of applying any wafer acceptance test (WAT) recipe to a test sample, calculating a recipe for a direct current (DC) final energy magnet (FEM), calculating a real energy of the DC FEM, verifying the tool energy shift, and obtaining a peak spectrum of the DC FEM.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: November 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiung Lin, Yao-Jen Yeh, Chia-Lin Ou, Cheng-En Lee, Hsuan-Pang Liu
  • Publication number: 20210314175
    Abstract: A PUF generator includes a difference generator circuit with first and second transistors having a first predetermined VT. The difference generator circuit is configured to provide a first output signal for generating a PUF signature based on respective turn on times of the first and second transistors. An amplifier includes a plurality of transistors having a second predetermined VT. The amplifier is configured to receive the first output signal and output the PUF signature.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 7, 2021
    Inventors: Shih-Lien Linus Lu, Jui-Che Tsai, Cheng-En Lee
  • Publication number: 20210306148
    Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.
    Type: Application
    Filed: November 30, 2020
    Publication date: September 30, 2021
    Inventors: Shih-Lien Linus Lu, Kun-hsi Li, Shih-Liang Wang, Jonathan Tsung-Yung Chang, Yu-Der Chih, Cheng-En Lee
  • Publication number: 20210250187
    Abstract: Systems and method are provided for determining a reliability of a physically unclonable function (PUF) cell of a device. A first signal is provided to a first branch of a PUF cell and a second signal is provided to a second branch of the PUF cell, the first and second signals being provided in synchronization. A base PUF cell value is determined based on an output of the PUF cell produced by the first signal and the second signal. A third signal is provided to the first branch and a fourth signal is provided to the second branch, the third signal and fourth signal being provided out of synchronization. A stressed PUF cell value is determined based on an output of the PUF cell produced by the third signal and the fourth signal. The PUF cell is determined to be unusable based on a difference between the PUF cell value and the stressed PUF cell value.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 12, 2021
    Inventors: Shih-Lien Linus Lu, Cheng-En Lee
  • Publication number: 20210248275
    Abstract: Systems and method are provided for determining a reliability of a physically unclonable function (PUF) cell of a device. One or more activation signals are provided to a PUF cell under a plurality of conditions. A PUF cell output provided by the PUF cell under each of the plurality of conditions is determined. A determination is made of a number of times the PUF cell output of the PUF cell is consistent. And a device classification value is determined based on the determined number of times for a plurality of PUF cells.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 12, 2021
    Inventors: Cheng-En Lee, Shih-Lien Linus Lu
  • Publication number: 20210043422
    Abstract: The present disclosure relates to a method includes generating ions with an ion source of an ion implantation apparatus based on an ion implantation recipe. The method includes accelerating the generated ions based on an ion energy setting in the ion implantation recipe and determining an energy spectrum of the accelerated ions. The method also includes analyzing a relationship between the determined energy spectrum and the ion energy setting. The method further includes adjusting at least one parameter of a final energy magnet (FEM) of the ion implantation apparatus based on the analyzed relationship.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 11, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsiung Lin, Cheng-En Lee, Chia-Lin Ou, Hsuan-Pang Liu, Yao-Jen Yeh
  • Patent number: 10818473
    Abstract: The present disclosure relates to a method includes generating ions with an ion source of an ion implantation apparatus based on an ion implantation recipe. The method includes accelerating the generated ions based on an ion energy setting in the ion implantation recipe and determining an energy spectrum of the accelerated ions. The method also includes analyzing a relationship between the determined energy spectrum and the ion energy setting. The method further includes adjusting at least one parameter of a final energy magnet (FEM) of the ion implantation apparatus based on the analyzed relationship.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsiung Lin, Cheng-En Lee, Chia-Lin Ou, Hsuan-Pang Liu, Yao-Jen Yeh
  • Publication number: 20200136840
    Abstract: A physically unclonable function (PUF) cell array includes a first PUF cell arranged in a first column in a first direction and a second PUF cell arranged in a second column in the first direction. The first PUF cell includes a first set of conductive structures extending in the first and a second direction. The second PUF cell includes a second set of conductive structures extending in the first and the second direction. The first PUF cell includes a first conductive structure and a second conductive structure extending in the second direction. The second PUF cell includes a third conductive structure and a fourth conductive structure extending in the second direction. The first and third conductive structure or the second and fourth conductive structure are symmetric to each other with respect to a central line of at least the first or second PUF cell extending in the second direction.
    Type: Application
    Filed: October 23, 2019
    Publication date: April 30, 2020
    Inventors: Cheng-En LEE, Shih-Lien Linus LU
  • Publication number: 20200058465
    Abstract: The present disclosure relates to a method includes generating ions with an ion source of an ion implantation apparatus based on an ion implantation recipe. The method includes accelerating the generated ions based on an ion energy setting in the ion implantation recipe and determining an energy spectrum of the accelerated ions. The method also includes analyzing a relationship between the determined energy spectrum and the ion energy setting. The method further includes adjusting at least one parameter of a final energy magnet (FEM) of the ion implantation apparatus based on the analyzed relationship.
    Type: Application
    Filed: August 13, 2019
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsiung LIN, Cheng-En LEE, Chia-Lin OU, Hsuan-Pang LIU, Yao-Jen YEH
  • Publication number: 20200043700
    Abstract: A method of tuning an ion implantation apparatus is disclosed. The method includes operations of applying any wafer acceptance test (WAT) recipe to a test sample, calculating a recipe for a direct current (DC) final energy magnet (FEM), calculating a real energy of the DC FEM, verifying the tool energy shift, and obtaining a peak spectrum of the DC FEM.
    Type: Application
    Filed: July 29, 2019
    Publication date: February 6, 2020
    Inventors: Yi-Hsiung LIN, Yao-Jen YEH, Chia-Lin OU, Cheng-En LEE, Hsuan-Pang LIU
  • Patent number: 10511309
    Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two inverters, at least one floating capacitor, at least two dynamic nodes, wherein the at least one floating capacitor is coupled between a first inverter at a first dynamic node and a second inverter at a second dynamic node; a PUF controller coupled to the PUF cell array, wherein the PUF controller is configured to charge the first dynamic nodes through the respective first inverters in the plurality of bit cells; and a finite state machine coupled to the PUF cell array configured to determine voltage levels on the second dynamic nodes through the respective second inverters in the plurality of bit cells to determine first logical states of the plurality of bit cells at at least one sampling time and generate a PUF signature.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Lien Linus Lu, Cheng-En Lee, Jui-Che Tsai
  • Publication number: 20190379381
    Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two inverters, at least one floating capacitor, at least two dynamic nodes, wherein the at least one floating capacitor is coupled between a first inverter at a first dynamic node and a second inverter at a second dynamic node; a PUF controller coupled to the PUF cell array, wherein the PUF controller is configured to charge the first dynamic nodes through the respective first inverters in the plurality of bit cells; and a finite state machine coupled to the PUF cell array configured to determine voltage levels on the second dynamic nodes through the respective second inverters in the plurality of bit cells to determine first logical states of the plurality of bit cells at at least one sampling time and generate a PUF signature.
    Type: Application
    Filed: December 21, 2018
    Publication date: December 12, 2019
    Inventors: Shih-Lien Linus LU, Cheng-En LEE, Jui-Che TSAI
  • Patent number: 10164646
    Abstract: A frequency generator includes: a PLL circuit, arranged to generate a first output clock and a first lock signal, the first output clock being generated based on an input clock, the first lock signal being used to indicate whether the first PLL circuit is locked, wherein when the first PLL circuit is locked, a frequency of the first output clock is N1 times a frequency of the input clock, and N1 is a positive integer; and a second PLL circuit, arranged to generate a second output clock and a second lock signal, the second output clock being generated based on the input clock, the second lock signal being used to indicate whether the second PLL circuit is locked, wherein when the second PLL circuit is locked, a frequency of the second output clock is N2 times the frequency of the input clock.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Lien Linus Lu, Cheng-En Lee
  • Patent number: 10164640
    Abstract: Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two inverters, at least one floating capacitor, at least two dynamic nodes, wherein the at least one floating capacitor is coupled between a first inverter at a first dynamic node and a second inverter at a second dynamic node; a PUF controller coupled to the PUF cell array, wherein the PUF controller is configured to charge the first dynamic nodes through the respective first inverters in the plurality of bit cells; and a finite state machine coupled to the PUF cell array configured to determine voltage levels on the second dynamic nodes through the respective second inverters in the plurality of bit cells to determine first logical states of the plurality of bit cells at at least one sampling time and generate a PUF signature.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Lien Linus Lu, Cheng-En Lee, Jui-Che Tsai
  • Publication number: 20120171956
    Abstract: A Bluetooth security system includes a master unit and a slave unit for matched connection by means of Bluetooth technology, an inquiry procedure adapted for monitoring the connection signal between the master unit and the slave unit, and an alarm device installed in each of the master unit and the slave unit and adapted for receiving a feedback signal from the inquiry procedure to output an alert message when the strength of the connection signal between the master unit and the slave unit drops below a predetermined threshold.
    Type: Application
    Filed: January 4, 2011
    Publication date: July 5, 2012
    Inventor: Cheng-En Lee
  • Publication number: 20120134868
    Abstract: A rotary sliding-vane compressor includes an air cylinder, a shaft eccentrically mounted in the air cylinder and rotatable by a motor, sliding vanes coupled to and movable back and forth along radially extending sliding grooves of the shaft, and an oil-gas separating device mounted in the air output port of the air cylinder. The shaft has an axial hole located on one end thereof and coupled to the output shaft of the motor, and two axle bushes respectively mounted on the two opposite ends. Each sliding vane comprises a metal substrate having evenly distributed through holes, and a covering material molded on the surface of the metal substrate and filled up the through holes and having a plurality of discharge grooves.
    Type: Application
    Filed: November 29, 2010
    Publication date: May 31, 2012
    Applicant: KINGSTON COMP CO., LTD.
    Inventors: Mao-Tu Lee, Cheng-En Lee, Wen-Shiang Tsai
  • Publication number: 20090233466
    Abstract: A surface-mounted circuit board module disposed on a system circuit board is disclosed. The surface-mounted circuit board module comprising a circuit board having at least an electronic component disposed thereon and a plurality of connectors. Each of the connectors comprises a first end portion at least partially embedded in the circuit board, a connecting portion connected with the first portion, and a second end portion extended and bent from the connecting portion. The second end portions are surface mounted on the system circuit board to electrically connect the electronic component of the circuit board and the system circuit board via the connectors.
    Type: Application
    Filed: June 6, 2008
    Publication date: September 17, 2009
    Applicant: DELTA ELECTRONICS, INC.
    Inventors: Cheng-En Lee, Chi-Ming Chin