Patents by Inventor Cheng-En Lee

Cheng-En Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250022945
    Abstract: Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a first source/drain feature and a second source/drain feature, a plurality of semiconductor layers vertically stacked and disposed between the first and second source/drain features, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, and an interfacial layer (IL) disposed between the gate electrode layer and one of the plurality of the semiconductor layers, wherein a topmost semiconductor layer of the plurality of the semiconductor layers has a first length, and the IL has a second length greater than the first length.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 16, 2025
    Inventors: Chung-En TSAI, Sheng-Syun WONG, Cheng-Han LEE, Chih-Yu MA, Shih-Chieh CHANG
  • Patent number: 12200148
    Abstract: Disclosed is a physical unclonable function generator circuit and method.
    Type: Grant
    Filed: January 12, 2024
    Date of Patent: January 14, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Lien Linus Lu, Cheng-En Lee
  • Patent number: 12169676
    Abstract: A physically unclonable function (PUF) cell array includes a first PUF cell in a first column in a first direction, a second PUF cell in a second column, and a first power rail. The first PUF cell includes a first set of conductive structures that include a first conductive structure extending in the second direction and a second conductive structure extending in the first direction. The second PUF cell includes a second set of conductive structures that include a third conductive structure extending in the second direction and a fourth conductive structure extending in the first direction. The first power rail overlapping a first boundary of the first and second PUF cell. At least the first and third conductive structure, or the second and the fourth conductive structure are symmetric to each other with respect to a central line of at least the first or second PUF cell.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: December 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-En Lee, Shih-Lien Linus Lu
  • Publication number: 20240348435
    Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.
    Type: Application
    Filed: April 2, 2024
    Publication date: October 17, 2024
    Inventors: Shih-Lien Linus Lu, Kun-hsi Li, Shih-Liang Wang, Jonathan Tsung-Yung Chang, Yu-Der Chih, Cheng-En Lee
  • Patent number: 12120214
    Abstract: The present invention provides an encryption determining method. The method includes the following steps: receiving a side channel signal; generating a filtered side channel signal by filtering noise within the side channel signal; generating a phasor signal by utilizing a filter to covert the filtered side channel signal; locating the encrypted segment by calculating a periodicity of the phasor signal utilizing a standard deviation window; extracting at least one encrypted characteristic from the encrypted segment; and generating an encryption analytic result by recognizing the at least one encrypted characteristic according to a characteristic recognition model; wherein the encryption analytic result includes a position of the encrypted segment within the side channel signal, and an encryption type corresponding to the side channel signal. The present invention is able to automatically and efficiently locate the encryption segment and analyze the encryption type corresponding to the side channel signal.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: October 15, 2024
    Assignee: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Jian-Wei Liao, Cheng-En Lee, Ting-Yu Lin
  • Publication number: 20240305481
    Abstract: A PUF generator includes a difference generator circuit with first and second transistors having a first predetermined VT. The difference generator circuit is configured to provide a first output signal for generating a PUF signature based on respective turn on times of the first and second transistors. An amplifier includes a plurality of transistors having a second predetermined VT. The amplifier is configured to receive the first output signal and output the PUF signature.
    Type: Application
    Filed: May 21, 2024
    Publication date: September 12, 2024
    Inventors: Shih-Lien Linus Lu, Jui-Che Tsai, Cheng-En Lee
  • Patent number: 12022014
    Abstract: A PUF generator includes a difference generator circuit with first and second transistors having a first predetermined VT. The difference generator circuit is configured to provide a first output signal for generating a PUF signature based on respective turn on times of the first and second transistors. An amplifier includes a plurality of transistors having a second predetermined VT. The amplifier is configured to receive the first output signal and output the PUF signature.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Lien Linus Lu, Jui-Che Tsai, Cheng-En Lee
  • Publication number: 20240154823
    Abstract: Disclosed is a physical unclonable function generator circuit and method.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Inventors: Shih-Lien Linus LU, Cheng-En LEE
  • Publication number: 20240143845
    Abstract: Systems and method are provided for determining a reliability of a physically unclonable function (PUF) cell of a device. One or more activation signals are provided to a PUF cell under a plurality of conditions. A PUF cell output provided by the PUF cell under each of the plurality of conditions is determined. A determination is made of a number of times the PUF cell output of the PUF cell is consistent. And a device classification value is determined based on the determined number of times for a plurality of PUF cells.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 2, 2024
    Inventors: Cheng-En Lee, Shih-Lien Linus Lu
  • Patent number: 11962693
    Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Lien Linus Lu, Kun-hsi Li, Shih-Liang Wang, Jonathan Tsung-Yung Chang, Yu-Der Chih, Cheng-En Lee
  • Publication number: 20240113856
    Abstract: The present invention provides an encryption determining method. The method includes the following steps: receiving a side channel signal; generating a filtered side channel signal by filtering noise within the side channel signal; generating a phasor signal by utilizing a filter to covert the filtered side channel signal; locating the encrypted segment by calculating a periodicity of the phasor signal utilizing a standard deviation window; extracting at least one encrypted characteristic from the encrypted segment; and generating an encryption analytic result by recognizing the at least one encrypted characteristic according to a characteristic recognition model; wherein the encryption analytic result includes a position of the encrypted segment within the side channel signal, and an encryption type corresponding to the side channel signal. The present invention is able to automatically and efficiently locate the encryption segment and analyze the encryption type corresponding to the side channel signal.
    Type: Application
    Filed: October 31, 2022
    Publication date: April 4, 2024
    Applicant: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Jian-Wei LIAO, Cheng-En LEE, Ting-Yu LIN
  • Patent number: 11947713
    Abstract: Systems and method are provided for determining a reliability of a physically unclonable function (PUF) cell of a device. One or more activation signals are provided to a PUF cell under a plurality of conditions. A PUF cell output provided by the PUF cell under each of the plurality of conditions is determined. A determination is made of a number of times the PUF cell output of the PUF cell is consistent. And a device classification value is determined based on the determined number of times for a plurality of PUF cells.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-En Lee, Shih-Lien Linus Lu
  • Patent number: 11902455
    Abstract: Disclosed is a physical unclonable function generator circuit and method.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Lien Linus Lu, Cheng-En Lee
  • Patent number: 11862429
    Abstract: An ion implantation system comprising: a sample platform; an ion gun; an electrostatic linear accelerator; a direct current (DC) final energy magnet (FEM); and a processor. The processor is programmed to control: a wafer acceptance test instrument, a DC recipe calculator, a DC real energy calculator, and a tool energy shift verifier. The wafer acceptance test instrument is configured to apply a wafer acceptance test (WAT) recipe to a test sample on the sample platform. The DC recipe calculator is configured to calculate a recipe for the DC FEM. The DC real energy calculator is configured to calculate a real energy of the DC FEM. The tool energy shift verifier is configured to verify a tool energy shift of the DC FEM. The ion implantation system is configured to tune the DC FEM based on the verified tool energy shift, and obtain a peak magnetic field of the DC FEM.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hsiung Lin, Yao-Jen Yeh, Chia-Lin Ou, Cheng-En Lee, Hsuan-Pang Liu
  • Publication number: 20230385459
    Abstract: Systems and method are provided for determining a reliability of a physically unclonable function (PUF) cell of a device. One or more activation signals are provided to a PUF cell under a plurality of conditions. A PUF cell output provided by the PUF cell under each of the plurality of conditions is determined. A determination is made of a number of times the PUF cell output of the PUF cell is consistent. And a device classification value is determined based on the determined number of times for a plurality of PUF cells.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Cheng-En Lee, Shih-Lien Linus Lu
  • Publication number: 20230376669
    Abstract: A physically unclonable function (PUF) cell array includes a first PUF cell in a first column in a first direction, a second PUF cell in a second column, and a first power rail. The first PUF cell includes a first set of conductive structures that include a first conductive structure extending in the second direction and a second conductive structure extending in the first direction. The second PUF cell includes a second set of conductive structures that include a third conductive structure extending in the second direction and a fourth conductive structure extending in the first direction. The first power rail overlapping a first boundary of the first and second PUF cell. At least the first and third conductive structure, or the second and the fourth conductive structure are symmetric to each other with respect to a central line of at least the first or second PUF cell.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Cheng-En LEE, Shih-Lien Linus LU
  • Patent number: 11783092
    Abstract: Systems and method are provided for determining a reliability of a physically unclonable function (PUF) cell of a device. One or more activation signals are provided to a PUF cell under a plurality of conditions. A PUF cell output provided by the PUF cell under each of the plurality of conditions is determined. A determination is made of a number of times the PUF cell output of the PUF cell is consistent. And a device classification value is determined based on the determined number of times for a plurality of PUF cells.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: October 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-En Lee, Shih-Lien Linus Lu
  • Patent number: 11727182
    Abstract: A physically unclonable function (PUF) cell array includes a first PUF cell in a first column in a first direction, and a first row in a second direction, and a second PUF cell in a second row in the second direction. The first PUF cell includes a first set of conductive structures extending in the first and second direction, being on a first metal layer, and including a first and a second conductive structure extending in the first direction. The second PUF cell includes a second set of conductive structures extending in the first direction and second direction, being on the first metal layer and including a third and a fourth conductive structure extending in the first direction. The first and third conductive structures, or the second and fourth conductive structures are symmetric to each other with respect to a central line of the first and second PUF cells.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-En Lee, Shih-Lien Linus Lu
  • Publication number: 20230121502
    Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.
    Type: Application
    Filed: December 9, 2022
    Publication date: April 20, 2023
    Inventors: Shih-Lien Linus Lu, Kun-hsi Li, Shih-Liang Wang, Jonathan Tsung-Yung Chang, Yu-Der Chih, Cheng-En Lee
  • Publication number: 20230106743
    Abstract: A PUF generator includes a difference generator circuit with first and second transistors having a first predetermined VT. The difference generator circuit is configured to provide a first output signal for generating a PUF signature based on respective turn on times of the first and second transistors. An amplifier includes a plurality of transistors having a second predetermined VT. The amplifier is configured to receive the first output signal and output the PUF signature.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 6, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Lien Linus Lu, Jui-Che Tsai, Cheng-En Lee