Patents by Inventor Cheng-Han Lee

Cheng-Han Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200368264
    Abstract: The present invention provides an alcohol extract of Ajuga taiwanensis Nakai ex Murata exhibits significant effects on inhibiting the senescence in human WI-38 lung fibroblasts and human dermal fibroblasts. Moreover, the alcohol extract of A. taiwanensis is able to suppress the expression of the cofilin-1, a protein involved in actin dynamics and cell morphology and found to be increased in senescent cells. Suppression effect of cell senescence by this herb extract is more efficient in mild concentration without over-inhibition of cell viability and growth.
    Type: Application
    Filed: May 26, 2020
    Publication date: November 26, 2020
    Inventors: Yi-Jang Lee, Yun-Lian Lin, Chung-Sheng Huang, Cheng-Han Tsai, Chun-Yuan Chang, Bing-Ze Lin, Yuan-Heng Tu, Wei-Hsiang Hsu, Pin-Ho Lo
  • Publication number: 20200365720
    Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Chih-Yu Ma, Zheng-Yang Pan, Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee
  • Patent number: 10840358
    Abstract: Semiconductor structures and method for forming the same are provide. The method includes forming a gate structure over a substrate and forming a recess in the substrate adjacent to the gate structure. The method further includes forming a doped region at a sidewall and a bottom surface of the recess and partially removing the doped region to modify a shape of the recess. The method further includes forming a source/drain structure over a remaining portion of the doped region.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee, Huai-Tei Yang
  • Patent number: 10833074
    Abstract: A process for manufacturing a semiconductor device and the resulting structure are presented. In an embodiment a source/drain region is grown. Once grown, the source/drain region is reshaped in order to remove facets. The reshaping may be performed using an etching process whereby a lateral etch rate of the source/drain region is larger than a vertical etch rate of the source/drain region.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Chang, Cheng-Han Lee, Yi-Min Huang
  • Publication number: 20200333332
    Abstract: Systems and methods to identify new protein targets of a chemical compound or its derivatives were described. The methods can be used for detection of new binding partners as long as the chemical compound can covalently bind to the protein targets. Once protein targets are resolved, information related to new protein targets can then be used to couple with real-world patient data such as adverse events, efficacy data, and disease correlation data to deduce real-world evidence. Systems collectively with all this information can aide clinical development and use of pharmaceutical drug. Methods are provided for detection of covalently bound phenyl vinyl sulfone (PVS) or its derivatives, and afatinib or its derivatives. Furthermore, generation of antiserum recognizing carrier bound PVS or carrier bound afatinib is described. PRMT1 is described as a new target of PVS and RRM1, RRM2, and NFKB are described as new targets of afatinib.
    Type: Application
    Filed: April 13, 2020
    Publication date: October 22, 2020
    Inventors: GEEN-DONG CHANG, MING-SHYUE LEE, CHENG-HAN YU
  • Publication number: 20200303548
    Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Cheng-Han Lee
  • Publication number: 20200295157
    Abstract: A method of forming a gate dielectric material includes forming a high-K dielectric material in a first region over a substrate, where forming the high-K dielectric material includes forming a first dielectric layer comprising hafnium over the substrate, and forming a second dielectric layer comprising lanthanum over the first dielectric layer.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: Shahaji B. More, Cheng-Han Lee, Zheng-Yang Pan, Shih-Chieh Chang, Chun-Chieh Wang
  • Patent number: 10734524
    Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yu Ma, Zheng-Yang Pan, Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee
  • Publication number: 20200243683
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate stack to partially cover a semiconductor structure. The method also includes forming a first semiconductor material over the semiconductor structure. The method further includes forming a second semiconductor material over the first semiconductor material. In addition, the method includes forming a third semiconductor material over the second semiconductor material. The first semiconductor material and the third semiconductor material together surround the second semiconductor material. The second semiconductor material has a greater dopant concentration than that of the first semiconductor material or that of the third semiconductor material.
    Type: Application
    Filed: April 17, 2020
    Publication date: July 30, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. MORE, Zheng-Yang PAN, Chun-Chieh WANG, Cheng-Han LEE, Shih-Chieh CHANG
  • Patent number: 10691268
    Abstract: A touch sensitive processing apparatus is used to detect at least one object approximating or touching a touch screen. The touch screen includes: multiple neighboring first electrodes and multiple neighboring second electrodes which are parallel to a first axis; and multiple neighboring third electrodes and multiple neighboring fourth electrodes which are parallel to a second axis. Each of the first electrodes intersects with the third electrodes to form multiple intersection areas, each of the second electrodes intersects with the fourth electrodes to form multiple intersection areas.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: June 23, 2020
    Assignee: EGALAX_EMPIA TECHNOLOGY INC.
    Inventors: Shang-Tai Yeh, Cheng-Han Lee
  • Publication number: 20200193405
    Abstract: Systems and methods for processing transactions using a digital payment platform.
    Type: Application
    Filed: December 12, 2019
    Publication date: June 18, 2020
    Inventors: Osama Bedier, Ray Tanaka, Victor Chau, Charles Feng, Cheng Han Lee, Lubab Al-Khawaja
  • Patent number: 10680106
    Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Cheng-Han Lee
  • Patent number: 10672886
    Abstract: A method of forming a gate dielectric material includes forming a high-K dielectric material in a first region over a substrate, where forming the high-K dielectric material includes forming a first dielectric layer comprising hafnium over the substrate, and forming a second dielectric layer comprising lanthanum over the first dielectric layer.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. More, Cheng-Han Lee, Zheng-Yang Pan, Shih-Chieh Chang, Chun-Chieh Wang
  • Publication number: 20200152742
    Abstract: The present disclosure describes an exemplary method to form p-type fully strained channel (PFSC) or an n-type fully strained channel (NFSC) that can mitigate epitaxial growth defects or structural deformations in the channel region due to processing. The exemplary method can include (i) two or more surface pre-clean treatment cycles with nitrogen trifluoride (NF3) and ammonia (NH3) plasma, followed by a thermal treatment; (ii) a prebake (anneal); and (iii) a silicon germanium epitaxial growth with a silicon seed layer, a silicon germanium seed layer, or a combination thereof.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. More, Huai-Tei YANG, Zheng-Yang PAN, Shih-Chieh CHANG, Chun-Chieh WANG, Cheng-Han Lee
  • Publication number: 20200135913
    Abstract: A semiconductor device includes a substrate; a fin protruding above the substrate, the fin including a compound semiconductor material that includes a semiconductor material and a first dopant, the first dopant having a different lattice constant than the semiconductor material, where a concentration of the first dopant in the fin changes along a first direction from an upper surface of the fin toward the substrate; a gate structure over the fin; a channel region in the fin and directly under the gate structure; and source/drain regions on opposing sides of the gate structure, the source/drain regions including a second dopant, where a concentration of the second dopant at a first location within the channel region is higher than that at a second location within the channel region, where the concentration of the first dopant at the first location is lower than that at the second location.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 30, 2020
    Inventors: Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee
  • Patent number: 10636909
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate stack to partially cover a semiconductor structure. The method also includes forming a first semiconductor material over the semiconductor structure. The method further includes forming a second semiconductor material over the first semiconductor material. In addition, the method includes forming a third semiconductor material over the second semiconductor material. The first semiconductor material and the third semiconductor material together surround the second semiconductor material. The second semiconductor material has a greater dopant concentration than that of the first semiconductor material or that of the third semiconductor material.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: April 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Chun-Chieh Wang, Cheng-Han Lee, Shih-Chieh Chang
  • Publication number: 20200124967
    Abstract: A method of supplying a chemical solution to a photolithography system. The chemical solution is pumped from a variable-volume buffer tank. The pumped chemical solution is dispensed in a spin-coater. The variable-volume buffer tank is refilled by emptying a storage container filled with the chemical solution into the variable-volume buffer tank.
    Type: Application
    Filed: December 17, 2019
    Publication date: April 23, 2020
    Inventors: Wen-Zhan Zhou, Heng-Jen Lee, Hsu-Yuan Liu, Yu-Chen Huang, Cheng-Han Wu, Shih-Che Wang, Ho-Yung David Hwang
  • Publication number: 20200118935
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Hong-Mao LEE, Huicheng CHANG, Chia-Han LAI, Chi-Hsuan NI, Cheng-Tung LIN, Huang-Yi HUANG, Chi-Yuan CHEN, Li-Ting WANG, Teng-Chun TSAI, Wei-Jung LIN
  • Publication number: 20200111911
    Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 9, 2020
    Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
  • Publication number: 20200105619
    Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.
    Type: Application
    Filed: June 3, 2019
    Publication date: April 2, 2020
    Inventors: Chien Lin, Kun-Yu Lee, Shahaji B. More, Cheng-Han Lee, Shih-Chieh Chang