Patents by Inventor Cheng-Han Lee

Cheng-Han Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11189924
    Abstract: An antenna structure includes a housing, a first feed source, a second feed source, a third feed source, and a radiating body. The first feed source is electrically coupled to a first radiating portion of the housing and adapted to provide an electric current to the first radiating portion. The second feed source is electrically coupled to the second radiating portion and adapted to provide an electric current to the second radiating portion. The radiating body is mounted within the housing and electrically coupled to the third feed source. The third feed source provides an electric current to the radiating body.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: November 30, 2021
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Cheng-Han Lee, Min-Hui Ho
  • Publication number: 20210351298
    Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 11, 2021
    Inventors: Yi-Min Huang, Shih-Chieh Chang, Cheng-Han Lee
  • Patent number: 11171220
    Abstract: A method of forming a gate dielectric material includes forming a high-K dielectric material in a first region over a substrate, where forming the high-K dielectric material includes forming a first dielectric layer comprising hafnium over the substrate, and forming a second dielectric layer comprising lanthanum over the first dielectric layer.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. More, Cheng-Han Lee, Zheng-Yang Pan, Shih-Chieh Chang, Chun-Chieh Wang
  • Patent number: 11113135
    Abstract: A memory device is provided. The memory device includes: a memory cell array; a monitoring circuit, and an event-checking circuit. The monitoring circuit is configured to detect one or more event parameters of the memory cell array, wherein the one or more event parameters correspond to one or more interrupt events of the memory cell array. The event-checking circuit is configured to determine whether to assert an interrupt signal according to the one or more event parameters detected by the monitoring circuit. In response to the event-checking circuit determining to assert the interrupt signal, a processor handles the one or more interrupt events of the memory device according to the interrupt signal.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: September 7, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Cheng-Han Lee, Chien-Ti Hou, Ying-Te Tu
  • Publication number: 20210273047
    Abstract: In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers and at least one of the spacer has width changes along vertical direction of device. At least one of the first semiconductor layers has a composition different from another of the first semiconductor layers.
    Type: Application
    Filed: July 21, 2020
    Publication date: September 2, 2021
    Inventors: Shu KUAN, Shahaji B. MORE, Chien LIN, Cheng-Han LEE, Shih-Chieh CHANG
  • Patent number: 11069810
    Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Min Huang, Shih-Chieh Chang, Cheng-Han Lee
  • Publication number: 20210193830
    Abstract: A semiconductor device includes a substrate; a fin protruding above the substrate, the fin including a compound semiconductor material that includes a semiconductor material and a first dopant, the first dopant having a different lattice constant than the semiconductor material, where a concentration of the first dopant in the fin changes along a first direction from an upper surface of the fin toward the substrate; a gate structure over the fin; a channel region in the fin and directly under the gate structure; and source/drain regions on opposing sides of the gate structure, the source/drain regions including a second dopant, where a concentration of the second dopant at a first location within the channel region is higher than that at a second location within the channel region, where the concentration of the first dopant at the first location is lower than that at the second location.
    Type: Application
    Filed: December 14, 2020
    Publication date: June 24, 2021
    Inventors: Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee
  • Publication number: 20210182822
    Abstract: Systems and methods for processing transactions using a digital payment platform.
    Type: Application
    Filed: February 25, 2021
    Publication date: June 17, 2021
    Inventors: Osama Bedier, Ray Tanaka, Victor Chau, Charles Feng, Cheng Han Lee, Lubab Al-Khawaja
  • Patent number: 11038256
    Abstract: An antenna structure includes a metal housing, a first radiator, and an isolating portion. The metal housing includes a front frame, a backboard, and a side frame. The side frame is positioned between the front frame and the backboard. The side frame defines a slot and the front frame defines a gap. The gap communicates with the slot and extends across the front frame. The metal housing is divided into at least a long portion and a short portion by the slot and the gap. The first radiator is positioned adjacent to the short portion. The isolating portion is connected to the first radiator to improve isolation between the short portion and the first radiator.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: June 15, 2021
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Cheng-Han Lee, Yi-Wen Hsu, Wei-Xuan Ye
  • Publication number: 20210175359
    Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.
    Type: Application
    Filed: February 22, 2021
    Publication date: June 10, 2021
    Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
  • Patent number: 11030033
    Abstract: A memory device is provided. The memory device includes: a memory cell array; a monitoring circuit, and an event-checking circuit. The monitoring circuit is configured to detect one or more event parameters of the memory cell array, wherein the one or more event parameters correspond to one or more interrupt events of the memory cell array. The event-checking circuit is configured to determine whether to assert an interrupt signal according to the one or more event parameters detected by the monitoring circuit. In response to the event-checking circuit determining to assert the interrupt signal, a processor handles the one or more interrupt events of the memory device according to the interrupt signal.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: June 8, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Cheng-Han Lee, Chien-Ti Hou, Ying-Te Tu
  • Patent number: 11024944
    Abstract: An antenna structure includes a metal housing, a first feed source, and a second feed source. The metal housing includes a front frame, a backboard, and a side frame. The side frame is positioned between the front frame and the backboard. The side frame defines a slot and the front frame defines a gap. The gap communicates with the slot and extends across the front frame. The metal housing is divided into at least a long portion and a short portion by the slot and the gap. The first feed source is electrically connected to the long portion and the second feed source is electrically connected to the short portion.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: June 1, 2021
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Cheng-Han Lee, Yi-Wen Hsu, Wei-Xuan Ye
  • Publication number: 20210135339
    Abstract: An antenna structure includes a metal housing, a first feed source, and a first radiator. The metal housing includes a front frame, a backboard, and a side frame. The side frame defines a slot and the front frame defines a gap. The metal housing is divided into at least a long portion and a short portion by the slot and the gap. The first radiator is positioned in the housing and includes a first radiating portion and a second radiating portion. One end of the first radiating portion is electrically connected to the first feed source and another end of the first radiating portion is spaced apart from the long portion. One end of the second radiating portion is electrically connected to the first feed source and another end of the second radiating portion is spaced apart from the short portion.
    Type: Application
    Filed: January 8, 2021
    Publication date: May 6, 2021
    Inventors: CHENG-HAN LEE, YI-WEN HSU, WEI-XUAN YE
  • Publication number: 20210118740
    Abstract: A semiconductor device and method includes: forming a gate stack over a substrate; growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si; growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having Ge impurities, the source/drain region free of the Ge impurities; depositing a metal layer over the semiconductor cap layer; annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the Ge impurities; and forming a metal contact electrically coupled to the silicide layer.
    Type: Application
    Filed: December 28, 2020
    Publication date: April 22, 2021
    Inventors: Shahaji B. More, Zheng-Yang Pan, Cheng-Han Lee, Shih-Chieh Chang
  • Patent number: 10970697
    Abstract: Systems and methods for processing transactions using a digital payment platform.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: April 6, 2021
    Assignee: Poynt Co.
    Inventors: Osama Bedier, Ray Tanaka, Victor Chau, Charles Feng, Cheng Han Lee, Lubab Al-Khawaja
  • Patent number: 10950603
    Abstract: A process for manufacturing a semiconductor device and the resulting structure are presented. In an embodiment a source/drain region is grown. Once grown, the source/drain region is reshaped in order to remove facets. The reshaping may be performed using an etching process whereby a lateral etch rate of the source/drain region is larger than a vertical etch rate of the source/drain region.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Chang, Cheng-Han Lee, Yi-Min Huang
  • Patent number: 10930781
    Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Shahaji B. More, Huai-Tei Yang, Shih-Chieh Chang, Shu Kuan, Cheng-Han Lee
  • Publication number: 20210050433
    Abstract: Semiconductor structures and method for forming the same are provide. The semiconductor structure includes a fin structure protruding from a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes an Arsenic-doped region formed in the fin structure and a source/drain structure formed over the Arsenic-doped region. In addition, a bottommost portion of the Arsenic-doped region is lower than a bottommost portion of the source/drain structure.
    Type: Application
    Filed: November 4, 2020
    Publication date: February 18, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shahaji B. MORE, Shih-Chieh CHANG, Cheng-Han LEE, Huai-Tei YANG
  • Patent number: 10923801
    Abstract: An antenna structure includes a metal housing, a first feed source, and a first radiator. The metal housing includes a front frame, a backboard, and a side frame. The side frame defines a slot and the front frame defines a gap. The metal housing is divided into at least a long portion and a short portion by the slot and the gap. The first radiator is positioned in the housing and includes a first radiating portion and a second radiating portion. One end of the first radiating portion is electrically connected to the first feed source and another end of the first radiating portion is spaced apart from the long portion. One end of the second radiating portion is electrically connected to the first feed source and another end of the second radiating portion is electrically connected to the short portion.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: February 16, 2021
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Cheng-Han Lee, Yi-Wen Hsu, Wei-Xuan Ye
  • Patent number: 10886614
    Abstract: An antenna structure includes a housing and a first feed source. The first feed source is electrically coupled to a first radiating portion of the housing and adapted to provide an electric current to the first radiating portion.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: January 5, 2021
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Cheng-Han Lee, Huo-Ying Chang