Patents by Inventor Cheng-Hsien Lee

Cheng-Hsien Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120143584
    Abstract: A computing device and a method for scattering parameter equivalent circuit reads a scattering parameter file from a storage device. A non-common-pole rational function of the scattering parameters in the scattering parameter file is created by applying a vector fitting algorithm to the scattering parameters. Passivity of the non-common-pole rational function is enforced if the non-common-pole rational function does not satisfy a determined passivity requirement.
    Type: Application
    Filed: October 25, 2011
    Publication date: June 7, 2012
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: WEN-LAING TSENG, YU-CHANG PAI, CHENG-HSIEN LEE, SHEN-CHUN LI, SHOU-KUO HSU
  • Patent number: 8191023
    Abstract: A system for selecting high speed serial signals includes a loading module, a layout selecting module, a data processing module, and an output module. The loading module reads a chip package length file; a layout selecting module reads a layout file and selects high speed serial signals preset by a user; the data processing module selects pins information of a start chip and a terminal chip transmit the selected high speed serial signals and finds the chip package length information, and analyzes interrupt points of the layout character from the start chip and outputs the chip package length information of the start chip, the layout length information, and the chip package length information of the terminal chip in sequence to the output module, to convert into a table and displays the table via a display device.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: May 29, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Shou-Kuo Hsu, Cheng-Hsien Lee
  • Publication number: 20120125679
    Abstract: A printed circuit board includes an insulating board, a pair of differential vias, and a number of wiring layers. A pair of via holes extends through opposite surfaces of the insulating board. The differential vias correspond to the pair of via holes. Each differential via includes a metal plated barrel and two via capture pads. The plated barrel is plated on the inner surface of the respective via hole, and terminates at each of the two opposite surfaces of the insulating board. The via capture pads are formed on the opposite surfaces of the insulating board around the openings of the via hole, and are electrically connected to the plated barrel. The wiring layers are arranged in the insulating board, and each define a clearance hole surrounding all of the via capture pads.
    Type: Application
    Filed: February 23, 2011
    Publication date: May 24, 2012
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: YUNG-CHIEH CHEN, CHENG-HSIEN LEE, PO-CHUAN HSIEH, SHOU-KUO HSU, SHIN-TING YEN
  • Publication number: 20120110540
    Abstract: In a method of optimizing parameters of electronic components on printed circuit boards (PCBs), a first experiment table for m variables of one type of parameter of P electronic components on a PCB is designed using n values of each variable and the RSM. P EHs of each first experiment are obtained by simulating, and P EH empirical formulas are computed according to the P EHs. A second experiment table for the m variables is designed using n? values of each variable and the full factorial design, and P EHs of each second experiment are computed using the P EH empirical formulas. Experiments, all the P EHs of which are greater than 1, are filtered from the second experiment tables, and an average EH of each filtered experiment is computed to pick an experiment the average EH of which is the greatest. The values of the m variables in the picked experiment are considered as optimized.
    Type: Application
    Filed: April 26, 2011
    Publication date: May 3, 2012
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: HSIAO-YUN SU, YING-TSO LAI, CHENG-HSIEN LEE
  • Publication number: 20120066660
    Abstract: In a method of managing process factors that influence electrical properties of printed circuit boards (PCBs), n process factors are arranged in an order according to different influence to one kind of electrical property of the PCBs. The different influence is determined by first experiments designed using the Taguchi method. M process factors that have important influence to the electrical property are obtained from the n process factors according to the order to design second experiments. A computing formula for the electrical property is fitted using the m process factors according to simulated results of the second experiments, and a variation range of each of the m process factors is computed according to the computing formula.
    Type: Application
    Filed: April 24, 2011
    Publication date: March 15, 2012
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: HSIAO-YUN SU, YING-TSO LAI, CHENG-HSIEN LEE
  • Patent number: 8124884
    Abstract: A printed circuit board (PCB) includes a positive differential signal line including first and second segments, a negative differential signal line including third and fourth segments, first and second connecting elements soldered on opposite surfaces of the PCB. The first segment and the fourth segment are located in a first straight line which has a first permittivity. The third segment and the second segment are located in a second straight line which has a second permittivity different from the first permittivity. The first connecting element is connected between the first segment and the second segment. The second connecting element is connected between the third segment and the fourth segment.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: February 28, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Yung-Chieh Chen, Cheng-Hsien Lee, Shou-Kuo Hsu
  • Publication number: 20120026902
    Abstract: A computing device and a method reads a circuit board layout file from a storage device, and selects a first signal transmission line from circuit board layout file as a target line. The computing device and method computes a distance between the target line and the aggressor line corresponding to each unit sample length. If the distance is more than or equal to a height of a sample region, the computing device and method defines the height of the sample region as a crosstalk space between the target line and the aggressor line corresponding to a unit sample length. Otherwise, if the distance is less than the height of the sample region, the computing device and method defines the distance as the crosstalk space between the target line and the aggressor line corresponding to the unit sample length.
    Type: Application
    Filed: December 7, 2010
    Publication date: February 2, 2012
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
    Inventors: YING-TSO LAI, SHI-PIAO LUO, CHENG-HSIEN LEE
  • Publication number: 20120017191
    Abstract: A computing device and a method involves selection of one or more transmission lines from a printed circuit board (PCB) layout file, reading a transmission line from the one or more selected transmission lines, and determining neighboring anti-pads of the read transmission line in the PCB layout file. The computing device and method further determine an actual distance between the read transmission line and a neighboring anti-pad. If the actual distance is less than a preset standard distance, the computing device and method determine that the read transmission line and the neighboring anti-pad do not satisfy design requirements, and highlight the read transmission line and the neighboring anti-pad, to prompt a user to amend design of the read transmission line and the neighboring anti-pad.
    Type: Application
    Filed: April 12, 2011
    Publication date: January 19, 2012
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD
    Inventors: HAN-LONG CHEN, SHI-PIAO LUO, CHENG-HSIEN LEE, CHIA-NAN PAI, SHOU-KUO HSU
  • Publication number: 20110301922
    Abstract: A simulation system for producing equivalent circuits reads data corresponding to a tabular W element format in a storage device, and adds data of the tabular W element format file using interpolation algorithm. A frequency-dependent transmission matrix is transformed into an N-port network matrix describing electrical properties of a multi-input and multi-output network. An N-port network matrix is transformed into a S-parameter matrix. A range of frequency of a s-parameter is determined and numbers of pole-residue, times for recursion and durable maximum system errors in the equivalent circuit is also determined. A a vector fitting algorithm is performed and a rational function matrix composed with s-parameters is produced, to produce a general SPICE equivalent circuit based on the generated rational function matrix.
    Type: Application
    Filed: December 2, 2010
    Publication date: December 8, 2011
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: WEN-LAING TSENG, CHENG-HSIEN LEE, SHEN-CHUN LI, YU-CHANG PAI, SHOU-KUO HSU
  • Publication number: 20110301923
    Abstract: A simulation system and method for generating equivalent circuits compatible with HSPICE reads data corresponding to N-port network system format in a storage device, and obtains S-parameter matrixes from the N-port network system. S-parameters in the S-parameter matrix that satisfy passivity are checked, and an interpolation algorithm to supplement S-parameters with passivity when some S-parameters not satisfy passivity is performed. Numbers of pole-residue, times for recursion and a tolerant system error of a rational function are generated for determining S-parameters. A rational function matrix composed of S-parameters is generated by performing a vector fitting algorithm, and an equivalent circuit is generated compatible with HSPICE format based on the generated rational function matrix.
    Type: Application
    Filed: December 8, 2010
    Publication date: December 8, 2011
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: WEN-LAING TSENG, CHENG-HSIEN LEE, SHEN-CHUN LI, YU-CHANG PAI, SHOU-KUO HSU
  • Publication number: 20110279927
    Abstract: A locked warning apparatus used for a handle of a hard disk drive bracket is described. The locked warning apparatus includes a locking base, a locking device, an upper cover assembly, and a pressing unit. The locking base has a clasping portion and an elastic protrusion. The locking device has a blocking portion. The clasping portion of the locking base is fastened to the locking device in a form of line-surface interface contact. The blocking portion reciprocates a back and forth motion on the elastic protrusion of the locking base to allow the locking device to retain either a lock status or an unlock status correspondingly. When the locking device retains the lock status, the locking device buckles the upper cover assembly. When the locking device retains the unlock status, the upper cover assembly can be ejected from the locking base by pushing the pressing unit.
    Type: Application
    Filed: August 27, 2010
    Publication date: November 17, 2011
    Applicant: QNAP SYSTEMS, INC.
    Inventor: Cheng-hsien Lee
  • Publication number: 20110271025
    Abstract: A computer motherboard includes a printed circuit board which includes a central processing unit (CPU) socket and a group of memory slots. The group of memory slots includes an in-line type memory slot and a surface mounted device (SMD) type memory slot. The in-line type memory slot includes a number of plated through holes. The SMD type memory slot is set between the in-line type memory slot and the CPU socket. The through holes of the in-line type memory slot are connected to the CPU socket through traces, pads of the SMD type memory slot are connected to corresponding through holes of the in-line type memory slot having the same pin definition.
    Type: Application
    Filed: June 28, 2010
    Publication date: November 3, 2011
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: YUNG-CHIEH CHEN, CHENG-HSIEN LEE, SHOU-KUO HSU, SHEN-CHUN LI, HSIEN-CHUAN LIANG, SHIN-TING YEN
  • Publication number: 20110265079
    Abstract: In an electronic device and a method for computing optimal parameters of an equalization filter, an output file, which comprises times and voltages of data points that represent a signal, of electronic circuit simulation software is loaded, and is read using the installed post-processing software. A time interval of outputs of the signal is obtained by selecting an output type of the signal. A parameter file which includes several sets of equalization parameters of the equalization filter is received, to select optimal equalization parameters for the equalization filter from the several sets of equalization parameters according to the times, the voltages, and the time interval, using a parameter formula y(n)=a*x(n)?b*x(n?1)?c*x(n?2).
    Type: Application
    Filed: February 28, 2011
    Publication date: October 27, 2011
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: CHENG-HSIEN LEE, SHOU-KUO HSU
  • Publication number: 20110231175
    Abstract: In an electronic device and a method of generating composite electrical signals, a plurality of post-processing software is installed. An output file, which comprises times and voltages of data points that represent an electrical signal, of an electronic circuit simulation software is loaded, and is read using the installed post-processing software. A time interval of outputs of the electrical signal is obtained by selecting an output type of the electrical signal. The worst bit combination of outputs of the electrical signal is analyzed according to the times, the voltage, and the time interval, and a composite electrical signal is generated according to the worst bit combination.
    Type: Application
    Filed: December 24, 2010
    Publication date: September 22, 2011
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: CHENG-HSIEN LEE, SHOU-KUO HSU
  • Publication number: 20110168437
    Abstract: A printed circuit board (PCB) includes a positive differential signal line including first and second segments, a negative differential signal line including third and fourth segments, first and second connecting elements soldered on opposite surfaces of the PCB. The first segment and the fourth segment are located in a first straight line which has a first permittivity. The third segment and the second segment are located in a second straight line which has a second permittivity different from the first permittivity. The first connecting element is connected between the first segment and the second segment. The second connecting element is connected between the third segment and the fourth segment.
    Type: Application
    Filed: January 25, 2010
    Publication date: July 14, 2011
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: YUNG-CHIEH CHEN, CHENG-HSIEN LEE, SHOU-KUO HSU
  • Publication number: 20110161259
    Abstract: A method for simplification of a matrix based boosting algorithm divides a feature set comprising a plurality of feature data into several subsets, and assigns a number to each subset. The method selects a plurality of number groups including N subsets randomly. The method further computes a value by boosting algorithm according to each of the number groups for obtaining an acceptable false positive value.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Applicants: HON HAI PRECISION INDUSTRY CO. LTD., MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventor: CHENG-HSIEN LEE
  • Publication number: 20110158539
    Abstract: A system and method for extracting feature data of dynamic objects selects sequential N frames of a video file up front, where N is a positive integer, and divides each of the N frames into N*N squares. The system and method further selects any n frames from the N frames, selects any n rows and n columns of the n frames to obtain n*n*n squares, where n is a positive integer. The system and method further extracts feature data from the video file by computing averages and differences for pixel values of the n*n*n squares.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventor: CHENG-HSIEN LEE
  • Publication number: 20110143922
    Abstract: A composition with catalyst particles for making a circuit pattern is provided. The composition includes an insulation material and a plurality of catalyst particles. The catalyst particles are distributed in the insulation material and not made of metal. When the composition is bathed in a chemical plating solution, a redox reaction takes place between some of the catalyst particles and the chemical plating solution so as to deposit a conductive pattern on the composition.
    Type: Application
    Filed: August 11, 2010
    Publication date: June 16, 2011
    Inventors: Cheng-Hsien Lee, Yi-Chun Liu
  • Publication number: 20110114379
    Abstract: A printed circuit board can support different connectors by selectively setting connection components on the printed circuit board without changing wiring of transmission lines or making new vias in the printed circuit board.
    Type: Application
    Filed: December 8, 2009
    Publication date: May 19, 2011
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: YUNG-CHIEH CHEN, CHENG-HSIEN LEE, SHOU-KUO HSU, SHEN-CHUN LI, HSIEN-CHUAN LIANG, SHIN-TING YEN
  • Patent number: 7916494
    Abstract: A printed circuit board includes a high-speed differential signal control chip, first to fourth coupling capacitor pads, first and second connector pads, first and second inductor pads, a number of transmission lines, a power pin, two sharing pads, and two selection pads. Two coupling capacitors can selectively connect the first and second coupling capacitor pads and the two sharing pads or between the third and fourth coupling capacitor pads and the two sharing pads, respectively. Two inductors can connect the first and second inductor pads and the two selection pads respectively, and the first and second inductor pads and the two selection pads can be void.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: March 29, 2011
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Yung-Chieh Chen, Cheng-Hsien Lee, Shou-Kuo Hsu, Shen-Chun Li, Hsien-Chuan Liang