Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.

Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a first thickness, a first dielectric material disposed adjacent the first conductive feature, and the first dielectric material has a second thickness greater than the first thickness. The structure further includes a second conductive feature disposed adjacent the first dielectric material, a first etch stop layer disposed on the first conductive feature, a second etch stop layer disposed on the first dielectric material, and a second dielectric material disposed on the first etch stop layer and the second etch stop layer. The second dielectric material is in contact with the first dielectric material.

Abstract: Methods and apparatus for a substrate processing chamber are provided herein. In some embodiments, a substrate processing chamber includes a chamber body having sidewalls defining an interior volume having a polygon shape; a selectively sealable elongated opening disposed in an upper portion of the chamber body for transferring one or more substrates into or out of the chamber body; a funnel disposed at a first end of the chamber body, wherein the funnel increases in size along a direction from an outer surface of the chamber body to the interior volume; and a pump port disposed at a second end of the chamber body opposite the funnel.

Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.

Abstract: A semiconductor structure includes a first metallization feature, a first dielectric structure over the first metallization feature, a second metallization feature embedded in the first dielectric structure, a via structure between the first metallization feature and the second metallization feature, and a first insulating layer between the first dielectric structure and the first metallization feature, and between the first dielectric structure and the via structure. The first metallization feature extends along a first direction, and the second metallization feature extends along a second direction different from the first direction. The first insulating layer covers first sidewalls of the via structure along the second direction.

Abstract: A method for manufacturing a semiconductor structure includes forming a trench in a dielectric structure; forming a spacer layer on a lateral surface of the dielectric structure exposed by the trench; after forming the spacer layer, forming a first electrically conductive feature in the trench; removing at least portion of the dielectric structure to form a recess; forming an etch stop layer in the recess and over the first electrically conductive feature; and after forming the etch stop layer, depositing a dielectric layer in the recess and over the first electrically conductive feature.

Abstract: A multilayer interconnect structure for integrated circuits includes a first dielectric layer over a substrate and a conductive line partially exposed over the first dielectric layer. The structure further includes an etch stop layer over both the first dielectric layer and the exposed conductive line, and a second dielectric layer over the etch stop layer. The second dielectric layer and the etch stop layer provide a via hole that partially exposes the conductive line. The structure further includes a via disposed in the via hole, and another conductive line disposed over the via and coupled to the conductive line through the via. Methods of forming the multilayer interconnect structure are also disclosed. The etch stop layer reduces the lateral and vertical etching of the first and second dielectric layers when the via hole is misaligned due to overlay errors.

Abstract: Methods of cleaning a substrate support comprise: introducing a cleaning gas into a processing chamber containing the substrate support; applying a radio frequency (RF) power to a remote plasma source that is in fluid communication with the processing chamber to establish a reactive etching plasma from the cleaning gas in the processing chamber; reacting deposits on the substrate support with the reactive etching plasma to form a by-products phase; and evacuating the by-products phase from the processing chamber.

Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a first conductive feature in a first dielectric layer, a second conductive feature aligned with and over the first conductive feature, a first insulation layer over the first dielectric layer and the second conductive feature, a second dielectric layer over the first insulating layer, and a contact via through the first insulation layer and the second dielectric layer.

Abstract: Methods and apparatus for supporting a substrate are provided herein. In some embodiments, a substrate support to support a substrate having a given diameter includes: a base ring having an inner diameter less than the given diameter, the base ring having a support surface configured to contact a first surface of the substrate and to form a seal between the support surface and the first surface of the substrate, when disposed atop the base ring; and a clamp ring having an inner diameter less than the given diameter, wherein the clamp ring includes a contact surface proximate the inner diameter configured to contact an upper surface of the substrate, when present, and wherein the clamp ring and the base ring are further configured to provide a bias force toward each other to clamp the substrate in the substrate support.

Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a first thickness, a first dielectric material disposed adjacent the first conductive feature, and the first dielectric material has a second thickness greater than the first thickness. The structure further includes a second conductive feature disposed adjacent the first dielectric material, a first etch stop layer disposed on the first conductive feature, a second etch stop layer disposed on the first dielectric material, and a second dielectric material disposed on the first etch stop layer and the second etch stop layer. The second dielectric material is in contact with the first dielectric material.

Abstract: A method for forming a semiconductor structure includes forming a first cap layer over a metal layer. The method also includes patterning the metal layer and the first cap layer to form openings exposing the gate structure, and forming a first dielectric layer in the openings, and patterning the first cap layer to form a via cap plug over the metal layer. The method also includes forming a second dielectric layer over the via cap plug and the metal layer, and forming a trench in the second dielectric material to expose the via cap plug. The method also includes removing the via cap plug to enlarge the trench and filling the trench with a conductive material.

Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.

Abstract: Methods and apparatus for substrate position calibration for substrate supports in substrate processing systems are provided herein. In some embodiments, a method for positioning a substrate on a substrate support includes: obtaining a plurality of backside pressure values corresponding to a plurality of different substrate positions on a substrate support by repeatedly placing a substrate in a position on the substrate support, and vacuum chucking the substrate to the substrate support and measuring a backside pressure; and analyzing the plurality of backside pressure values to determine a calibrated substrate position.

Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.

Abstract: Methods and apparatus for substrate position calibration for substrate supports in substrate processing systems are provided herein. In some embodiments, a method for positioning a substrate on a substrate support includes: obtaining a plurality of backside pressure values corresponding to a plurality of different substrate positions on a substrate support by repeatedly placing a substrate in a position on the substrate support, and vacuum chucking the substrate to the substrate support and measuring a backside pressure; and analyzing the plurality of backside pressure values to determine a calibrated substrate position.

Abstract: A method for forming a semiconductor structure includes forming a first cap layer over a metal layer. The method also includes patterning the metal layer and the first cap layer to form openings exposing the gate structure, and forming a first dielectric layer in the openings, and patterning the first cap layer to form a via cap plug over the metal layer. The method also includes forming a second dielectric layer over the via cap plug and the metal layer, and forming a trench in the second dielectric material to expose the via cap plug. The method also includes removing the via cap plug to enlarge the trench and filling the trench with a conductive material.

Abstract: Two-piece shutter disk assemblies for use in process chambers are provided herein. In some embodiments, a shutter disk assembly for use in a process chamber includes an upper disk member having a top surface and a bottom surface, wherein a central alignment recess is formed in a center of the bottom surface, and a lower carrier member having a solid base having an upper support surface, wherein the upper support surface includes a first central self-centering feature disposed in the recess formed in the center of the bottom surface and an annular outer alignment feature that protrudes upward from a top surface of the lower carrier and forms a pocket, wherein the upper disk member is disposed in the pocket.

Abstract: Embodiments of an electrostatic chuck are provided herein. In some embodiments an electrostatic chuck includes an electrode, a dielectric body having a disk shape and covering the electrode, the dielectric body including a central region and a peripheral region, and the dielectric body including a lower surface having a central opening and an upper surface having a first opening in the central region and a plurality of second openings in the peripheral region, wherein the upper surface includes a plurality of protrusions and a diameter of each of the plurality of second openings is greater than 25.0 mils, and gas distribution channels that extend from the lower surface to the upper surface to define a plenum within the dielectric body.

Abstract: Fabrication of gallium nitride-based light devices with physical vapor deposition (PVD)-formed aluminum nitride buffer layers is described. Process conditions for a PVD AlN buffer layer are also described. Substrate pretreatments for a PVD aluminum nitride buffer layer are also described. In an example, a method of fabricating a buffer layer above a substrate involves pre-treating a surface of a substrate. The method also involves, subsequently, reactive sputtering an aluminum nitride (AlN) layer on the surface of the substrate from an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-based gas or plasma.