Patents by Inventor Cheng-Hsiung Tsai

Cheng-Hsiung Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210082804
    Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
  • Patent number: 10950475
    Abstract: Methods and apparatus for processing a substrate are provided. The apparatus, for example, can include a process chamber comprising a chamber body defining a processing volume and having a view port coupled to the chamber body; a substrate support disposed within the processing volume and having a support surface to support a substrate; and an infrared temperature sensor (IRTS) disposed outside the chamber body adjacent the view port to measure a temperature of the substrate when being processed in the processing volume, the IRTS movable relative to the view port for scanning the substrate through the view port.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: March 16, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Vinodh Ramachandran, Ananthkrishna Jupudi, Cheng-Hsiung Tsai, Yueh Sheng Ow, Preetham P. Rao, Ribhu Gautam, Prashant Agarwal
  • Publication number: 20210057244
    Abstract: Methods and apparatus for processing a substrate are provided. The apparatus, for example, can include a process chamber comprising a chamber body defining a processing volume and having a view port coupled to the chamber body; a substrate support disposed within the processing volume and having a support surface to support a substrate; and an infrared temperature sensor (IRTS) disposed outside the chamber body adjacent the view port to measure a temperature of the substrate when being processed in the processing volume, the IRTS movable relative to the view port for scanning the substrate through the view port.
    Type: Application
    Filed: August 20, 2019
    Publication date: February 25, 2021
    Inventors: VINODH RAMACHANDRAN, ANANTHKRISHNA JUPUDI, CHENG-HSIUNG TSAI, YUEH SHENG OW, PREETHAM P. RAO, RIBHU GAUTAM, PRASHANT AGARWAL
  • Publication number: 20210057333
    Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a first conductive feature in a first dielectric layer, a second conductive feature aligned with and over the first conductive feature, a first insulation layer over the first dielectric layer and the second conductive feature, a second dielectric layer over the first insulating layer, and a contact via through the first insulation layer and the second dielectric layer.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Inventors: Cheng-Hsiung Tsai, Ming-Han Lee, Chung-Ju Lee
  • Publication number: 20210035856
    Abstract: A multilayer interconnect structure for integrated circuits includes a first dielectric layer over a substrate and a conductive line partially exposed over the first dielectric layer. The structure further includes an etch stop layer over both the first dielectric layer and the exposed conductive line, and a second dielectric layer over the etch stop layer. The second dielectric layer and the etch stop layer provide a via hole that partially exposes the conductive line. The structure further includes a via disposed in the via hole, and another conductive line disposed over the via and coupled to the conductive line through the via. Methods of forming the multilayer interconnect structure are also disclosed. The etch stop layer reduces the lateral and vertical etching of the first and second dielectric layers when the via hole is misaligned due to overlay errors.
    Type: Application
    Filed: October 19, 2020
    Publication date: February 4, 2021
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee, Shau-Lin Shue, Tien-I Bao
  • Patent number: 10861742
    Abstract: A multilayer interconnect structure for integrated circuits includes a first dielectric layer over a substrate and a conductive line partially exposed over the first dielectric layer. The structure further includes an etch stop layer over both the first dielectric layer and the exposed conductive line, and a second dielectric layer over the etch stop layer. The second dielectric layer and the etch stop layer provide a via hole that partially exposes the conductive line. The structure further includes a via disposed in the via hole, and another conductive line disposed over the via and coupled to the conductive line through the via. Methods of forming the multilayer interconnect structure are also disclosed. The etch stop layer reduces the lateral and vertical etching of the first and second dielectric layers when the via hole is misaligned due to overlay errors.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee, Shau-Lin Shue, Tien-I Bao
  • Publication number: 20200378006
    Abstract: Methods and apparatus for a substrate processing chamber are provided herein. In some embodiments, a substrate processing chamber includes a chamber body having sidewalls defining an interior volume having a polygon shape; a selectively sealable elongated opening disposed in an upper portion of the chamber body for transferring one or more substrates into or out of the chamber body; a funnel disposed at a first end of the chamber body, wherein the funnel increases in size along a direction from an outer surface of the chamber body to the interior volume; and a pump port disposed at a second end of the chamber body opposite the funnel.
    Type: Application
    Filed: May 28, 2019
    Publication date: December 3, 2020
    Inventors: RIBHU GAUTAM, ANANTHKRISHNA JUPUDI, TUCK FOONG KOH, PREETHAM P. RAO, VINODH RAMACHANDRAN, YUEH SHENG OW, YUICHI WADA, CHENG-HSIUNG TSAI, KAI LIANG LIEW
  • Patent number: 10851453
    Abstract: Methods and apparatus for detecting a shutter disk assembly in a process chamber using a number of sensors. A first, second, and third sensor in a shutter housing for a shutter disk assembly provide indications of a status of the shutter disk assembly. The indications are used in part to determine the operational status of the shutter disk assembly along with process information from a process controller. The operational status is then used to alter a process of the process chamber when necessary.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: December 1, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Cheng-Hsiung Tsai, Ananthkrishna Jupudi, Eiji Asahina, Sarath Babu
  • Publication number: 20200286738
    Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a patterning process; and forming a second plurality of trenches in the first layer by another patterning process, resulting in combined trench patterns in the first layer. A first trench of the second plurality connects two trenches of the first plurality. The method further includes forming dielectric spacer features on sidewalls of the combined trench patterns. A space between two opposing sidewalls of the first trench is completely filled by the dielectric spacer features and another space between two opposing sidewalls of one of the two trenches is partially filled by the dielectric spacer features.
    Type: Application
    Filed: May 22, 2020
    Publication date: September 10, 2020
    Inventors: RU-GUN LIU, CHENG-HSIUNG TSAI, CHUNG-JU LEE, CHIH-MING LAI, CHIA-YING LEE, JYU-HORNG SHIEH, KEN-HSIEN HSIEH, MING-FENG SHIEH, SHAU-LIN SHUE, SHIH-MING CHANG, TIEN-I BAO, TSAI-SHENG GAU
  • Patent number: 10763086
    Abstract: Apparatus for plasma processing of semiconductor substrates. Aspects of the apparatus include an upper shield with a gas diffuser arranged at a center of the upper shield. The gas diffuser and upper shield admit a process gas to a processing chamber in a laminar manner. A profile of the upper shield promotes radial expansion of the process gas and radial travel of materials etched from a surface of the substrates. Curvatures of the upper shield direct the etched materials to a lower shield with reduced depositing of etched materials on the upper shield. The lower shield also includes curved surfaces that direct the etched materials toward slots that enable the etched materials to exit from the process chamber with reduced depositing on the lower shield.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: September 1, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Bonnie T. Chia, Cheng-hsiung Tsai
  • Publication number: 20200230782
    Abstract: Embodiments of methods and apparatus for cleaning contaminants from a substrate are disclosed herein. In some embodiments, a substrate cleaning apparatus includes: a substrate support to support a substrate along an edge of the substrate, wherein the substrate further includes a first side and an opposing second side having contaminants disposed on the second side; a showerhead disposed a first distance of about 1.5 mm to about 4.4 mm opposite the substrate support and facing the first side of the substrate; and one or more nozzles disposed a second distance of about 1 inch to about 2 inches beneath the substrate support to discharge a mixture of solid and gaseous carbon dioxide toward the contaminants on the second side of the substrate, and wherein the one or more nozzles have an angle of about 20 to about 40 degrees.
    Type: Application
    Filed: April 2, 2020
    Publication date: July 23, 2020
    Inventors: Pulkit AGARWAL, Bonnie T. CHIA, Song-Moon SUH, Cheng-Hsiung TSAI, Dhritiman Subha KASHYAP, Xiaoxiong YUAN, Eric RIESKE
  • Patent number: 10711348
    Abstract: Apparatus for improving substrate temperature uniformity in a substrate processing chamber are provided herein. In some embodiments, a cover plate for a substrate processing chamber includes: an outer portion; and a raised inner portion having a thermally emissive layer, wherein a thermal emissivity of the thermally emissive layer varies across the thermally emissive layer.
    Type: Grant
    Filed: March 7, 2015
    Date of Patent: July 14, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Cheng-Hsiung Tsai, Youqun Dong, Manjunatha Koppa
  • Patent number: 10704147
    Abstract: Embodiments of the present disclosure are directed process kits for use with an in-chamber heater and substrate rotating mechanism. In some embodiments consistent with the present disclosure, a process kit for use with a rotatable substrate support heater pedestal for supporting a substrate in a process chamber may include an upper edge ring including a top ledge and a skirt the extends downward from the top ledge, a lower edge ring that at least partially supports the upper edge ring and aligns the upper edge ring with the substrate support heater pedestal, a bottom plate disposed on a bottom of the process chamber that supports the upper edge ring when the substrate support heater pedestal is in a lowered non-processing position, and a shadow ring that couples with the upper edge ring when the substrate support heater pedestal is in a raised processing position.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: July 7, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Muhammad M. Rasheed, Muhannad Mustafa, Hamid Tavassoli, Steven V Sansoni, Cheng-Hsiung Tsai, Vikash Banthia
  • Publication number: 20200194243
    Abstract: Embodiments of a process kit are provided herein. In some embodiments, a process kit includes a deposition ring configured to be disposed on a substrate support, the deposition ring including an annular band configured to rest on a lower ledge of the substrate support, the annular band having an upper surface and a lower surface, the lower surface including a step between a radially inner portion and a radially outer portion; an inner lip extending upwards from the upper surface of the annular band and adjacent an inner surface of the annular band, wherein a depth between an upper surface of the annular band and a horizontal portion of the upper surface of the inner lip is between about 6.0 mm and about 12.0 mm; a channel disposed radially outward of and beneath the annular band; and an outer lip extending upwardly and disposed radially outward of the channel.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: DAVID GUNTHER, CHENG-HSIUNG TSAI, KIRANKUMAR NEELASANDRA SAVANDAIAH
  • Publication number: 20200185247
    Abstract: Embodiments of an electrostatic chuck are provided herein. In some embodiments an electrostatic chuck includes an electrode, a dielectric body having a disk shape and covering the electrode, the dielectric body including a central region and a peripheral region, and the dielectric body including a lower surface having a central opening and an upper surface having a first opening in the central region and a plurality of second openings in the peripheral region, wherein the upper surface includes a plurality of protrusions and a diameter of each of the plurality of second openings is greater than 25.0 mils, and gas distribution channels that extend from the lower surface to the upper surface to define a plenum within the dielectric body.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 11, 2020
    Inventors: BONNIE T CHIA, ROSS MARSHALL, TOMOHARU MATSUSHITA, CHENG-HSIUNG TSAI
  • Patent number: 10665467
    Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a first patterning process; and forming a second plurality of trenches in the first layer by second patterning process, wherein a first trench of the second plurality merges with two trenches of the first plurality to form a continuous trench. The method further includes forming spacer features on sidewalls of the first and second pluralities of trenches. The spacer features have a thickness. A width of the first trench is equal to or less than twice the thickness of the spacer features thereby the spacer features merge inside the first trench.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ru-Gun Liu, Cheng-Hsiung Tsai, Chung-Ju Lee, Chih-Ming Lai, Chia-Ying Lee, Jyu-Horng Shieh, Ken-Hsien Hsieh, Ming-Feng Shieh, Shau-Lin Shue, Shih-Ming Chang, Tien-I Bao, Tsai-Sheng Gau
  • Publication number: 20190326152
    Abstract: Methods and apparatus for supporting a substrate are provided herein. In some embodiments, a substrate support to support a substrate having a given diameter includes: a base ring having an inner diameter less than the given diameter, the base ring having a support surface configured to contact a first surface of the substrate and to form a seal between the support surface and the first surface of the substrate, when disposed atop the base ring; and a clamp ring having an inner diameter less than the given diameter, wherein the clamp ring includes a contact surface proximate the inner diameter configured to contact an upper surface of the substrate, when present, and wherein the clamp ring and the base ring are further configured to provide a bias force toward each other to clamp the substrate in the substrate support.
    Type: Application
    Filed: April 18, 2019
    Publication date: October 24, 2019
    Inventors: CHANG KE, BONNIE CHIA, SONG-MOON SUH, CHENG-HSIUNG TSAI, YUANHONG GUO, LEI ZHOU, DAVID LANGTRY
  • Publication number: 20190326154
    Abstract: Two-piece shutter disk assemblies for use in process chambers are provided herein. In some embodiments, a shutter disk assembly for use in a process chamber includes an upper disk member having a top surface and a bottom surface, wherein a central alignment recess is formed in a center of the bottom surface, and a lower carrier member having a solid base having an upper support surface, wherein the upper support surface includes a first central self-centering feature disposed in the recess formed in the center of the bottom surface and an annular outer alignment feature that protrudes upward from a top surface of the lower carrier and forms a pocket, wherein the upper disk member is disposed in the pocket.
    Type: Application
    Filed: April 15, 2019
    Publication date: October 24, 2019
    Inventors: CHENG-HSIUNG TSAI, ANANTHKRISHNA JUPUDI, SARATH BABU
  • Patent number: D888903
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 30, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: David Gunther, Cheng-Hsiung Tsai, Kirankumar Neelasandra Savandaiah
  • Patent number: D893441
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: August 18, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Shreesha Yogish Rao, Mukund Sundararajan, Cheng-Hsiung Tsai, Manjunatha P. Koppa, Steven Sansoni