Patents by Inventor Cheng-Hsiung Tsai

Cheng-Hsiung Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device manufacturing methods
    Patent number: 9768031
    Abstract: Semiconductor device manufacturing methods are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a first pattern in a hard mask using a first lithography process, and forming a second pattern in the hard mask using a second lithography process. A protective layer is formed over the hard mask. Portions of the hard mask and portions of the protective layer are altered using a self-aligned double patterning (SADP) method.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Cheng-Hsiung Tsai
  • Metal lines for interconnect structure and method of manufacturing same
    Patent number: 9735052
    Abstract: A method for fabricating a semiconductor device includes forming a dielectric layer over a substrate, forming an etch-stop-layer (ESL) over the dielectric layer, forming a first patterned hard mask (HM) defining a first trench over the ESL, forming a second trench extending through the ESL and the dielectric layer. The second trench is adjacent the first trench. The method also includes filling in the first trench and the second trench with a first material layer, extending the first trench through the ESL and the dielectric layer while the first material layer is filled in the second trench to form an extended first trench, forming a first metal line within the extended first trench, forming a capping layer over the first metal line and removing a portion of the first metal line to form a first cut by using the ESL and the first material layer as an etch mask.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: August 15, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsiung Tsai, Carlos H. Diaz, Chung-Ju Lee, Shau-Lin Shue, Tien-I Bao, Yung-Hsu Wu, Hsin-Ping Chen
  • Self-Aligned Double Spacer Patterning Process
    Publication number: 20170200641
    Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, forming a set of mandrels over the first hard mask layer, and forming a first spacer layer over the set of mandrels and the first hard mask layer. The method further includes forming a second spacer layer over the first spacer layer, patterning the first spacer layer and the second spacer layer to form a mask pattern, and patterning the first hard mask layer using the mask pattern as a mask.
    Type: Application
    Filed: March 27, 2017
    Publication date: July 13, 2017
    Inventors: Cheng-Hsiung Tsai, Yung-Hsu Wu, Tsung-Min Huang, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • APPARATUS AND METHOD FOR REDUCING SUBSTRATE SLIDING IN PROCESS CHAMBERS
    Publication number: 20170186631
    Abstract: Methods and apparatus for processing a substrate are disclosed herein. In some embodiments, an apparatus for processing a substrate includes: a substrate support having a substrate supporting surface including an electrically insulating coating; a substrate lift mechanism including a plurality of lift pins configured to move between a first position disposed beneath the substrate supporting surface and a second position disposed above the substrate supporting surface; and a connector configured to selectively provide an electrical connection between the substrate support and the substrate lift mechanism before the plurality of lift pins reach a plane of the substrate supporting surface.
    Type: Application
    Filed: March 13, 2017
    Publication date: June 29, 2017
    Inventors: SRISKANTHARAJAH THIRUNAVUKARASU, KIRANKUMAR SAVANDAIAH, CHENG-HSIUNG TSAI, KAI LIANG LIEW
  • Interconnect structure having an etch stop layer over conductive lines
    Patent number: 9685368
    Abstract: A multilayer interconnect structure for integrated circuits includes a first dielectric layer over a substrate and a conductive line partially exposed over the first dielectric layer. The structure further includes an etch stop layer over both the first dielectric layer and the exposed conductive line, and a second dielectric layer over the etch stop layer. The second dielectric layer and the etch stop layer provide a via hole that partially exposes the conductive line. The structure further includes a via disposed in the via hole, and another conductive line disposed over the via and coupled to the conductive line through the via. Methods of forming the multilayer interconnect structure are also disclosed. The etch stop layer reduces the lateral and vertical etching of the first and second dielectric layers when the via hole is misaligned due to overlay errors.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: June 20, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee, Shau-Lin Shue, Tien-I Bao
  • METHOD OF SPACER PATTERNING TO FORM A TARGET INTEGRATED CIRCUIT PATTERN
    Publication number: 20170162435
    Abstract: A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches.
    Type: Application
    Filed: February 17, 2017
    Publication date: June 8, 2017
    Inventors: Chieh-Han WU, Cheng-Hsiung TSAI, Chung-Ju LEE, Ming-Feng SHIEH, Ru-Gun LIU, Shau-Lin SHUE, Tien-I BAO
  • Semiconductor integrated circuit with nano gap
    Patent number: 9653349
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A substrate having a dielectric layer over it is provided. A block co-polymer (BCP) layer is deposited over the dielectric layer. The BCP layer is then annealed to form a first polymer nanostructures surrounded by a second polymer nanostructures over the dielectric layer. The second polymer nanostructure is selectively etched using the first polymer nanostructure as an etch mask to form a nano-block. The dielectric layer is selectively etched using the nano-block as an etch mask to form a nano-trench. The nano-trenched is sealed to form a nano-air-gap.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsiung Tsai, Chieh-Han Wu, Chung-Ju Lee, Shau-Lin Shue
  • Structure and method for interconnection
    Patent number: 9627215
    Abstract: A method includes providing a substrate having a first conductive feature in a first dielectric material layer; forming a first etch stop layer on the first dielectric material layer, wherein the first etch stop layer is formed of a high-k dielectric material; forming a second etch stop layer on the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; forming a pattered mask layer on the second dielectric material layer; forming a first trench in the second dielectric material layer and the second etch stop layer; removing a portion of the first etch stop layer through the first trench to thereby form a second trench, wherein removing the portion of the first etch stop layer includes applying a solution to the portion of the first etch stop layer; and forming a second conductive feature in the second trench.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hua Huang, Cheng-Hsiung Tsai, Chung-Ju Lee, Cherng-Shiaw Tsai
  • Integrated circuit interconnects and methods of making same
    Patent number: 9627256
    Abstract: A dielectric layer is formed on a substrate and patterned to form an opening. The opening is filled and the dielectric layer is covered with a metal layer. The metal layer is thereafter planarized so that the metal layer is co-planar with the top of the dielectric layer. The metal layer is etched back a predetermined thickness from the top of the dielectric layer to expose the inside sidewalls thereof. A sidewall barrier layer is formed on the sidewalls of the dielectric layer. A copper-containing layer is formed over the metal layer, the dielectric layer, and the sidewall barrier layers. The copper-containing layer is etched to form interconnect features, wherein the etching stops at the sidewall barrier layers at approximately the juncture of the sidewall of the dielectric layer and the copper-containing layer and does not etch into the underlying metal layer.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee, Bo-Jiun Lin, Hsien-Chang Wu
  • Method for Interconnect Scheme
    Publication number: 20170103915
    Abstract: A method for fabricating a semiconductor device includes forming a dielectric layer over a substrate, forming an etch-stop-layer (ESL) over the dielectric layer, forming a first patterned hard mask (HM) defining a first trench over the ESL, forming a second trench extending through the ESL and the dielectric layer. The second trench is adjacent the first trench. The method also includes filling in the first trench and the second trench with a first material layer, extending the first trench through the ESL and the dielectric layer while the first material layer is filled in the second trench to form an extended first trench, forming a first metal line within the extended first trench, forming a capping layer over the first metal line and removing a portion of the first metal line to form a first cut by using the ESL and the first material layer as an etch mask.
    Type: Application
    Filed: October 12, 2015
    Publication date: April 13, 2017
    Inventors: Cheng-Hsiung Tsai, Carlos H. Diaz, Chung-Ju Lee, Shau-Lin Shue, Tien-I Bao, Yung-Hsu Wu, Hsin-Ping Chen
  • Pad design for electrostatic chuck surface
    Patent number: 9613846
    Abstract: Embodiments are directed to an electrostatic chuck surface having minimum contact area features. More particularly, embodiments of the present invention provide an electrostatic chuck assembly having a pattern of raised, elongated surface features for providing reduced particle generation and reduced wear of substrates and chucking devices.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: April 4, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Govinda Raj, Cheng-Hsiung Tsai, Robert T. Hirahara, Kadthala R. Narendrnath, Manjunatha Koppa, Ross Marshall
  • Structure and Method for Interconnection
    Publication number: 20170092580
    Abstract: A method includes providing a substrate having a first conductive feature in a first dielectric material layer; forming a first etch stop layer on the first dielectric material layer, wherein the first etch stop layer is formed of a high-k dielectric material; forming a second etch stop layer on the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; forming a pattered mask layer on the second dielectric material layer; forming a first trench in the second dielectric material layer and the second etch stop layer; removing a portion of the first etch stop layer through the first trench to thereby form a second trench, wherein removing the portion of the first etch stop layer includes applying a solution to the portion of the first etch stop layer; and forming a second conductive feature in the second trench.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: CHIEN-HUA HUANG, CHENG-HSIUNG TSAI, CHUNG-JU LEE, CHERNG-SHIAW TSAI
  • Self-aligned double spacer patterning process
    Patent number: 9607850
    Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, forming a set of mandrels over the first hard mask layer, and forming a first spacer layer over the set of mandrels and the first hard mask layer. The method further includes forming a second spacer layer over the first spacer layer, patterning the first spacer layer and the second spacer layer to form a mask pattern, and patterning the first hard mask layer using the mask pattern as a mask.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: March 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsiung Tsai, Yung-Hsu Wu, Tsung-Min Huang, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Apparatus and method for reducing substrate sliding in process chambers
    Patent number: 9595464
    Abstract: Methods and apparatus for processing a substrate are disclosed herein. In some embodiments, an apparatus for processing a substrate includes: a substrate support having a substrate supporting surface including an electrically insulating coating; a substrate lift mechanism including a plurality of lift pins configured to move between a first position disposed beneath the substrate supporting surface and a second position disposed above the substrate supporting surface; and a connector configured to selectively provide an electrical connection between the substrate support and the substrate lift mechanism before the plurality of lift pins reach a plane of the substrate supporting surface.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: March 14, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Sriskantharajah Thirunavukarasu, Kirankumar Savandaiah, Cheng-Hsiung Tsai, Kai Liang Liew
  • Spacer Etching Process for Integrated Circuit Design
    Publication number: 20170069505
    Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a first patterning process; and forming a second plurality of trenches in the first layer by second patterning process, wherein a first trench of the second plurality merges with two trenches of the first plurality to form a continuous trench. The method further includes forming spacer features on sidewalls of the first and second pluralities of trenches. The spacer features have a thickness. A width of the first trench is equal to or less than twice the thickness of the spacer features thereby the spacer features merge inside the first trench.
    Type: Application
    Filed: November 21, 2016
    Publication date: March 9, 2017
    Inventors: RU-GUN LIU, CHENG-HSIUNG TSAI, CHUNG-JU LEE, CHIH-MING LAI, CHIA-YING LEE, JYU-HORNG SHIEH, KEN-HSIEN HSIEH, MING-FENG SHIEH, SHAU-LIN SHUE, SHIH-MING CHANG, TIEN-I BAO, TSAI-SHENG GAU
  • Method for interconnect scheme
    Patent number: 9589890
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first dielectric layer over a substrate, forming a first trench in the first dielectric layer, forming a metal line in the first trench, removing a first portion of the metal line to form a second trench and removing a second portion of the metal line to form a third trench. A third portion of the metal line is disposed between the second and third trenches. The method also includes forming a second dielectric layer in the second and third trenches.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: March 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chieh Yao, Carlos H. Diaz, Cheng-Hsiung Tsai, Chung-Ju Lee, Chien-Hua Huang, Hsi-Wen Tien, Shau-Lin Shue, Tien-I Bao, Yung-Hsu Wu
  • Method of spacer patterning to form a target integrated circuit pattern
    Patent number: 9576814
    Abstract: A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chung-Ju Lee, Ming-Feng Shieh, Ru-Gun Liu, Shau-Lin Shue, Tien-I Bao
  • Interconnect structure and method of forming the same
    Patent number: 9564397
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature and a second conductive feature in the LK dielectric layer; a first spacer along a first sidewall of the first conductive feature; a second spacer along a second sidewall of the second conductive feature, wherein the second sidewall of the second conductive feature faces the first sidewall of the first conductive feature; an air gap between the first spacer and the second spacer; and a third conductive feature over the first conductive feature, wherein the third conductive feature is connected to the first conductive feature.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: February 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee, Hai-Ching Chen, Shau-Lin Shue, Tien-I Bao
  • Method for Interconnect Scheme
    Publication number: 20170025346
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first dielectric layer over a substrate, forming a first trench in the first dielectric layer, forming a metal line in the first trench, removing a first portion of the metal line to form a second trench and removing a second portion of the metal line to form a third trench. A third portion of the metal line is disposed between the second and third trenches. The method also includes forming a second dielectric layer in the second and third trenches.
    Type: Application
    Filed: July 20, 2015
    Publication date: January 26, 2017
    Inventors: Hsin-Chieh Yao, Carlos H. Diaz, Cheng-Hsiung Tsai, Chung-Ju Lee, Chien-Hua Huang, Hsi-Wen Tien, Shau-Lin Shue, Tien-I Bao, Yung-Hsu Wu
  • Plasma cleaning apparatus and method
    Patent number: 9552968
    Abstract: Embodiments of the present invention generally include an apparatus for plasma cleaning and a method for plasma cleaning. The apparatus can include a lid body having a first surface for facing a pedestal during cleaning and a second surface opposite the first surface and substantially parallel to the first surface, the second surface having a first indentation sized to receive a magnet assembly, one or more handles coupled to the second surface of the lid body, and the magnet assembly resting in the first indentation. The method can include removing a sputtering target from the processing chamber, sealing the processing chamber, introducing a gas into the processing chamber, applying an RF bias to a pedestal within the processing chamber, maintaining the pedestal at a substantially constant temperature, and removing material from the pedestal to clean the pedestal.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: January 24, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Martin Deehan, Matt Cheng-Hsiung Tsai, Nan Lu, David T. Or, Mei Chang