Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.

Abstract: A plating system and a method thereof are disclosed. The plating system performs a N-stage plating drilling filling process in which a M-th stage plating drilling filling process with a M-th current density is performed on a hole of a substrate for a M-th plating time to form a M-th plating layer on the to-be-plated layer, wherein N is a positive integer equal to or greater than 3, and M is a positive integer positive integer in a range of 1 to N. Therefore, the technical effect of providing a higher drilling filling rate than conventional plating filling technology under a condition that a total thickness of plating layers is fixed can be achieved.

Abstract: An organic optoelectronic device comprises a first electrode, an active layer and a second electrode. Active layer materials of the active layer comprise a block conjugated polymer materials which includes a structure of formula I: The polymer 1 is a p-type polymer with high energy gap, and the polymer 1 comprises a first electron donor and a first electron acceptor arranged alternately. The polymer 2 is a p-type polymer with low energy gap, and the polymer 2 comprises a second electron donor and a second electron acceptor arranged alternately. Wherein, o and p>0. The organic optoelectronic device of the present invention transfers carriers through the polymer 2 with low energy gap, and suppresses the recombination probability of carriers through the polymer 1 with high energy gap, thereby reducing the leakage current of the organic optoelectronic device.

Abstract: A computing system performs shared cache allocation to allocate cache resources to groups of tasks. The computing system monitors the bandwidth at a memory hierarchy device that is at a next level to the cache in a memory hierarchy of the computing system. The computing system estimates a change in dynamic power from a corresponding change in the bandwidth before and after the cache resources are allocated. The allocation of the cache resources are adjusted according to an allocation policy that receives inputs including the estimated change in the dynamic power and a performance indication of task execution.

Abstract: A computing system performs partial cache deactivation. The computing system estimates the leakage power of a cache based on operating conditions of the cache including voltage and temperature. The computing system further identifies a region of the cache as a candidate for deactivation based on cache hit counts. The computing system then adjusts the size of the region for the deactivation based on the leakage power and a bandwidth of a memory hierarchy device. The memory hierarchy device is at the next level to the cache in a memory hierarchy of the computing system.

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Abstract: A device includes a first transistor, a second transistor, and a dielectric structure. The first transistor is over a substrate and has a first gate structure. The second transistor is over the substrate and has a second gate structure. The dielectric structure is between the first gate structure and the second gate structure. The dielectric structure has a width increasing from a bottom position of the dielectric structure to a first position higher than the bottom position of the dielectric structure. A width of the first gate structure is less than the width of the dielectric structure at the first position.

Abstract: A physiological signal measurement device is disclosed. In some implementations, the physiological signal measurement device includes a fixing element, a rack, a first sensor, and a second sensor. The fixing element is configured to be fixed on a limb of a user. The rack is configured to engage the fixing element and includes a first end and a second end distal to the first end. The first sensor is disposed on the first end of the rack. The sensor is disposed on the second end of the rack. The first end of the rack has a first stiffness, the second end of the rack has a second stiffness, and the first stiffness is higher than the second stiffness.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

Abstract: A micro fluid actuator includes an orifice layer, a flow channel layer, a substrate, a chamber layer, a vibration layer, a lower electrode layer, a piezoelectric actuation layer and an upper electrode layer, which are stacked sequentially. An outflow aperture, a plurality of first inflow apertures and a second inflow aperture are formed in the substrate by an etching process. A storage chamber is formed in the chamber layer by the etching process. An outflow opening and an inflow opening are formed in the orifice layer by the etching process. An outflow channel, an inflow channel and a plurality of columnar structures are formed in the flow channel layer by a lithography process. By providing driving power which have different phases to the upper electrode layer and the lower electrode layer, the vibration layer is driven to displace in a reciprocating manner, so as to achieve fluid transportation.

Abstract: A MEMS pump includes a first substrate, a first oxide layer, a second substrate, a second oxide layer, a third substrate and a piezoelectric element sequentially stacked to form the entire structure of the MEMS pump. The first substrate has a first thickness and at least one inlet aperture. The first oxide layer has at least one fluid inlet channel and a convergence chamber, wherein the fluid inlet channel communicates with the convergence chamber and the inlet aperture. The second substrate has a second thickness and a through hole, and the through hole is misaligned with the inlet aperture and communicates with the convergence chamber. The second oxide layer has a first chamber with a concave central portion. The third substrate has a third thickness and a plurality of gas flow channels, wherein the gas flow channels are misaligned with the through hole.

Abstract: A micro channel structure includes a substrate, a supporting layer, a valve layer, a second insulation layer, a vibration layer and a bonding-pad layer. A flow channel is formed on the substrate. A conductive part and a movable part are formed on the supporting layer and the valve layer, respectively. A first chamber is formed at the interior of a base part and communicates to the hollow aperture. A supporting part is formed on the second insulation layer. A second chamber is formed at the interior of the supporting layer and communicates to the first chamber through the hollow aperture. A suspension part is formed on the vibration layer. By providing driving power sources having different phases to the bonding-pad layer, the suspension part moves upwardly and downwardly, and a relative displacement is generated between the movable part and the conductive part, to achieve fluid transportation.

Abstract: A micro-electromechanical systems pump includes a first substrate, a first oxide layer, a second substrate, and a piezoelectric element. The first oxide layer is stacked on the first substrate. The second substrate is combined with the first substrate, and the second substrate includes a silicon wafer layer, a second oxide layer, and a silicon material layer. The silicon wafer layer has an actuation portion. The actuation portion is circular and has a maximum stress value and an actuation stress value. The second oxide layer is formed on the silicon wafer layer. The silicon material layer is located at the second oxide layer and is combined with the first oxide layer. The piezoelectric element is stacked on the actuation portion, and has a piezoelectric stress value. The maximum stress value is greater than the actuation stress value, and the actuation stress value is greater than the piezoelectric stress value.

Abstract: A narrow type inkjet print head chip is disclosed and includes a silicon substrate, an active component layer and a passive component layer. The active component layer is stacked on the silicon substrate and includes plural ESD protection units, plural encoder switches, plural discharge protection units and plural heater switches. The ESD protection units, the encoder switches, the discharge protection units and the heater switches are disposed in each of at least two high-precision regions of the active component layer. The corresponding positions and quantities of these components are the same in the at least two high-precision regions. The passive component layer is stacked on the active component layer and includes plural heaters, plural electrode pads, plural encoders and plural circuit traces. The circuit traces are electrically connected to the ESD protection units, the encoder switches, the heater switches, the heaters, the electrode pads and the encoders.

Abstract: The present disclosure provides a control method of a fluid device. The control method includes the steps of (a) providing the fluid device, which includes a plurality of flow guiding units manufactured by a micro-electro-mechanical-system process; (b) dividing the flow guiding units into a plurality of groups, which are electrically connected to and controlled by a control module; and (c) generating a driving signal by the control module for a corresponding one of the groups, wherein the control module generates a high level signal to a specific one of the groups, so that the flow guiding units of the specific one of the groups are driven to transport fluid, and thereby controlling the fluid device to discharge a specific amount of fluid.

Abstract: An actuating and sensing module includes a substrate, at least one sensor and at least one actuating device. The at least one sensor is disposed on the substrate. The at least one actuating device is disposed on the substrate, and has at least one guiding channel between the actuating device and the substrate. The at least one guiding channel is disposed on one side of the at least one sensor. When the at least one actuating device is enabled, a fluid is transferred to the at least one sensor through the at least one guiding channel, so that the fluid is sensed by the at least one sensor.

Abstract: A manufacturing method of narrow type inkjet print head chip is provided and includes steps of: (S1) providing a silicon substrate; (S2) arranging and disposing an active component layer by utilizing a first type photomask on at least two high-precision regions of each of a plurality of inkjet print head chip regions on the silicon substrate; (S3) arranging and disposing a passive component layer by utilizing a second type photomask on the active component layer; and (S4) cutting the silicon substrate according to the inkjet print head chip regions so as to form the plurality of narrow type inkjet print head chips.

Abstract: A narrow type inkjet print head chip is disclosed and includes a silicon substrate, an active component layer and a passive component layer. The active component layer is stacked on the silicon substrate and includes plural ESD protection units, plural encoder switches, plural discharge protection units and plural heater switches. The ESD protection units, the encoder switches, the discharge protection units and the heater switches are disposed in each of at least two high-precision regions of the active component layer. The corresponding positions and quantities of these components are the same in the at least two high-precision regions. The passive component layer is stacked on the active component layer and includes plural heaters, plural electrode pads, plural encoders and plural circuit traces. The circuit traces are electrically connected to the ESD protection units, the encoder switches, the heater switches, the heaters, the electrode pads and the encoders.

Abstract: A micro fluid actuator includes a first substrate, a chamber layer, a vibration layer, a first metal layer, a piezoelectric actuation layer, a second metal layer, a second substrate, an inlet layer, a resonance layer and an aperture array plate. The first substrate includes a plurality of first outflow apertures and a plurality of second outflow apertures. The chamber layer includes a storage chamber. The second metal layer includes an upper electrode pad and a lower electrode pad. While driving power having different phase charges is provided to the upper electrode pad and the lower electrode pad to drive and control the vibration layer to displace in a reciprocating manner, the fluid is inhaled from the exterior through the inlet layer, converged to the storage chamber, compressed and pushes out the aperture array plate, and then is discharged out from the micro fluid actuator to achieve fluid transportation.