Patents by Inventor Cheng Nan Chang
Cheng Nan Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240127988Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a first polymer and a conductive filler. The first polymer consists of polyvinylidene difluoride (PVDF), and PVDF exists in different phases such as ?-PVDF, ?-PVDF and ?-PVDF. The total amount of ?-PVDF, ?-PVDF and ?-PVDF is calculated as 100%, and the amount of ?-PVDF accounts for 48% to 55%. The conductive filler has a metal-ceramic compound.Type: ApplicationFiled: March 2, 2023Publication date: April 18, 2024Inventors: HSIU-CHE YEN, YUNG-HSIEN CHANG, CHENG-YU TUNG, Chia-Yuan Lee, CHEN-NAN LIU, Yao-Te Chang, FU-HUA CHU
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Publication number: 20240127989Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a first polymer and a conductive filler. The first polymer consists of polyvinylidene difluoride (PVDF), and PVDF exists in different phases such as ?-PVDF, ?-PVDF and ?-PVDF. The total amount of ?-PVDF, ?-PVDF and ?-PVDF is calculated as 100%, and the amount of ?-PVDF accounts for 33% to 42%.Type: ApplicationFiled: January 25, 2023Publication date: April 18, 2024Inventors: CHIA-YUAN LEE, CHENG-YU TUNG, HSIU-CHE YEN, CHEN-NAN LIU, YUNG-HSIEN CHANG, YAO-TE CHANG, FU-HUA CHU
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Patent number: 10387047Abstract: A memory circuit includes a plurality of banks and a controller, each bank of the plurality of banks includes a plurality of segments, and each segment of the plurality of segments includes a plurality of bit lines and a plurality of word lines. A word line switch corresponding to a word line of a segment of the memory circuit is turned on and data are written into memory cells of the segment coupled to a plurality of bit lines of the segment and corresponding to the word line in turn after the controller enables an active command corresponding to the word line. When the controller enables at least one copy row write command, the data are simultaneously written into memory cells sharing a plurality of sense amplifiers with the plurality of bit lines of the segment and corresponding to at least one another word line.Type: GrantFiled: November 21, 2016Date of Patent: August 20, 2019Assignee: Etron Technology, Inc.Inventors: Chun Shiah, Cheng-Nan Chang, Yu-Hui Sung
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Patent number: 10037787Abstract: A circuit for outputting information of a memory circuit during a self-refresh mode includes a driver. The driver is coupled to a self-refresh control circuit and a self-refresh address counter. The driver is used for driving a plurality of pads of the memory circuit to output information of a plurality of inner signals corresponding to a self-refresh mode signal, and output information of addresses of a plurality of word lines of the memory circuit when the self-refresh mode signal and a test mode signal are enabled and the memory circuit enters the self-refresh mode. Each word line of the plurality of word lines corresponds to an inner signal of the plurality of inner signals.Type: GrantFiled: September 6, 2017Date of Patent: July 31, 2018Assignee: Etron Technology, Inc.Inventors: Chun Shiah, Ho-Yin Chen, Cheng-Nan Chang
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Publication number: 20180068693Abstract: A circuit for outputting information of a memory circuit during a self-refresh mode includes a driver. The driver is coupled to a self-refresh control circuit and a self-refresh address counter. The driver is used for driving a plurality of pads of the memory circuit to output information of a plurality of inner signals corresponding to a self-refresh mode signal, and output information of addresses of a plurality of word lines of the memory circuit when the self-refresh mode signal and a test mode signal are enabled and the memory circuit enters the self-refresh mode. Each word line of the plurality of word lines corresponds to an inner signal of the plurality of inner signals.Type: ApplicationFiled: September 6, 2017Publication date: March 8, 2018Inventors: Chun Shiah, Ho-Yin Chen, Cheng-Nan Chang
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Publication number: 20170147211Abstract: A memory circuit includes a plurality of banks and a controller, each bank of the plurality of banks includes a plurality of segments, and each segment of the plurality of segments includes a plurality of bit lines and a plurality of word lines. A word line switch corresponding to a word line of a segment of the memory circuit is turned on and data are written into memory cells of the segment coupled to a plurality of bit lines of the segment and corresponding to the word line in turn after the controller enables an active command corresponding to the word line. When the controller enables at least one copy row write command, the data are simultaneously written into memory cells sharing a plurality of sense amplifiers with the plurality of bit lines of the segment and corresponding to at least one another word line.Type: ApplicationFiled: November 21, 2016Publication date: May 25, 2017Inventors: Chun Shiah, Cheng-Nan Chang, Yu-Hui Sung
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Patent number: 8755236Abstract: A latch system applied to a plurality of banks of a memory circuit includes a front latch circuit and a plurality of rear latch circuit. The front latch circuit is used for receiving a datum and a front latch enabling signal, and generating and outputting an intermediate signal according to the datum and the front latch enabling signal. Each rear latch circuit of the plurality of rear latch circuits is coupled to an output terminal of the front latch circuit for receiving the intermediate signal, and generating and outputting a rear latch datum to a corresponding bank of the plurality of banks according to the intermediate signal and a corresponding rear latch enabling signal, where only one rear latch enabling signal is enabled at any time.Type: GrantFiled: February 3, 2012Date of Patent: June 17, 2014Assignee: Etron Technology, Inc.Inventors: Chun Shiah, Shi-Huei Liu, Cheng-Nan Chang
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Publication number: 20120230124Abstract: A latch system applied to a plurality of banks of a memory circuit includes a front latch circuit and a plurality of rear latch circuit. The front latch circuit is used for receiving a datum and a front latch enabling signal, and generating and outputting an intermediate signal according to the datum and the front latch enabling signal. Each rear latch circuit of the plurality of rear latch circuits is coupled to an output terminal of the front latch circuit for receiving the intermediate signal, and generating and outputting a rear latch datum to a corresponding bank of the plurality of banks according to the intermediate signal and a corresponding rear latch enabling signal, where only one rear latch enabling signal is enabled at any time.Type: ApplicationFiled: February 3, 2012Publication date: September 13, 2012Inventors: Chun Shiah, Shi-Huei Liu, Cheng-Nan Chang
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Publication number: 20120167019Abstract: A mask revision recording circuit for a memory circuit includes a mask recording module and a reading unit. The mask recording module includes a plurality of mask recording units, and a layout of each mask recording unit corresponds to all masks of a layout of the memory circuit. The reading unit is coupled to the mask recording module for reading information of the mask recording module corresponding to a mask revision of the memory circuit according to a clock and an enable signal.Type: ApplicationFiled: March 16, 2011Publication date: June 28, 2012Inventors: Shi-Huei Liu, Yung-Hsing Chen, Cheng-Nan Chang
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Patent number: 7969253Abstract: A VCO includes a reference current module and a clock signal generating module. The reference current module generates a reference current according to a reference voltage. The clock signal generating module generates a clock signal according to the reference current. The reference current module utilizes the negative feed-back mechanism to keep the generated reference current at the predetermined size without being changed with the variation of the process and the bias source.Type: GrantFiled: July 20, 2009Date of Patent: June 28, 2011Assignee: Etron Technology, Inc.Inventors: Chun Shiah, Cheng-Nan Chang, Yu-Sheng Lai
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Publication number: 20100073062Abstract: A VCO includes a reference current module and a clock signal generating module. The reference current module generates a reference current according to a reference voltage. The clock signal generating module generates a clock signal according to the reference current. The reference current module utilizes the negative feed-back mechanism to keep the generated reference current at the predetermined size without being changed with the variation of the process and the bias source.Type: ApplicationFiled: July 20, 2009Publication date: March 25, 2010Inventors: Chun Shiah, Cheng-Nan Chang, Yu-Sheng Lai
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Patent number: 7508726Abstract: A signal sensing circuit and a semiconductor memory device using the same are provided. The signal sensing circuit comprises a sense amplifier, a kick transistor, a first control transistor, a second control transistor, a pre-charge circuit, and a recovery circuit. The kick transistor is used to pull up the operation voltage of the sense amplifier to improve the small signal sensing speed of the sense amplifier. After the signal is sensed, the recovery circuit will pull down the operation voltage of the sense amplifier to the standard level. In the present invention, the small signal sensing speed is greatly improved and the operation voltage of sense amplifier is kept away from the saturated level.Type: GrantFiled: May 10, 2007Date of Patent: March 24, 2009Assignee: Etron Technology Inc.Inventors: Chun Shiah, Chun-Peng Wu, Cheng-Nan Chang
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Publication number: 20080279026Abstract: A signal sensing circuit and a semiconductor memory device using the same are provided. The signal sensing circuit comprises a sense amplifier, a kick transistor, a first control transistor, a second control transistor, a pre-charge circuit, and a recovery circuit. The kick transistor is used to pull up the operation voltage of the sense amplifier to improve the small signal sensing speed of the sense amplifier. After the signal is sensed, the recovery circuit will pull down the operation voltage of the sense amplifier to the standard level. In the present invention, the small signal sensing speed is greatly improved and the operation voltage of sense amplifier is kept away from the saturated level.Type: ApplicationFiled: May 10, 2007Publication date: November 13, 2008Inventors: Chun Shiah, Chun-Peng Wu, Cheng-Nan Chang
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Publication number: 20080203594Abstract: A method for fabricating an aeration stone is disclosed, which abandoned activated sludge, red soil and an alkaline metal oxide are separately dried firstly and then cracked, and next the cracked abandoned activated sludge, red soil and alkaline metal oxide are separately sieved to obtain smaller grains thereof, and then the grains are separately ground into fine particles thereof and are mixed to be a mixture. Next, the mixture is molded into a green aeration stone. Next, the green aeration stone is fired at a high temperature and then cooled down to obtain a finished aeration stone. Therefore, the present invention recycles the abandoned sludge of wastewater treatment works to reduce the secondary pollution of abandoned sludge.Type: ApplicationFiled: December 13, 2007Publication date: August 28, 2008Inventors: Cheng-Nan CHANG, Wen-fang Su
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Patent number: 7014710Abstract: A method of growing single crystal Gallium Nitride on silicon substrate is disclosed including: removing oxide layer of silicon substrate, growing buffer layer of Silicon Carbon Nitride (SiCN), and growing single crystalline Gallium Nitride thin film, characterized in that a buffer layer of SiCN is grown to avoid lattice mismatch which appears when Gallium Nitride is grown directly on silicon substrate, and that Rapid Thermal Chemical Vapor Deposition is adopted to grow SiCN buffer layer, and that Metalorganic Chemical Vapor Deposition is adopted to grow single crystalline GaN thin film.Type: GrantFiled: July 8, 2003Date of Patent: March 21, 2006Assignee: National Cheng-Kung UniversityInventors: Yean Kuen Fang, Wen Rong Chang, Shyh Fann Ting, Hon Kuan, Cheng Nan Chang
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Publication number: 20040074437Abstract: A method of growing single crystal Gallium Nitride on silicon substrate is disclosed including: removing oxide layer of silicon substrate, growing buffer layer of Silicon Carbon Nitride (SiCN), and growing single crystalline Gallium Nitride thin film, characterized in that a buffer layer of SiCN is grown to avoid lattice mismatch which appears when Gallium Nitride is grown directly on silicon substrate, and that Rapid Thermal Chemical Vapor Deposition is adopted to grow SiCN buffer layer, and that Metalorganic Chemical Vapor Deposition is adopted to grow single crystalline GaN thin film.Type: ApplicationFiled: July 8, 2003Publication date: April 22, 2004Inventors: Yean Kuen Fang, Wen Rong Chang, Shyh Fann Ting, Hon Kuan, Cheng Nan Chang