Patents by Inventor Cheng-wei Chen

Cheng-wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210013234
    Abstract: An electronic device is provided. The electronic device includes a substrate, a first gate circuit, a second gate circuit, a signal line, and a shielding layer. The substrate includes a display area and a peripheral area. The first gate circuit is disposed in the peripheral area. The second gate circuit is disposed in the peripheral area. The signal line is coupled between the first gate circuit and the second gate circuit. The signal line includes a specific line segment, and the specific line segment overlaps the display area. The shielding layer is disposed in the display area. The shielding layer overlaps the specific line segment.
    Type: Application
    Filed: June 22, 2020
    Publication date: January 14, 2021
    Inventors: Yu-Che CHANG, Li-Wei SUNG, Cheng-Tso CHEN, Hui-Min HUANG, Chia-Min YEH, Hung-Hsun CHEN
  • Publication number: 20200411374
    Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hsiang-Wei Liu, Tai-I Yang, Chia-Tien Wu, Hai-Ching Chen, Shau-Lin Shue
  • Publication number: 20200410949
    Abstract: A display device includes a substrate, a plurality of scan lines and a plurality of data lines. The data lines respectively have a first segment that overlaps one of the scan lines and a second segment that is located between adjacent two of the scan lines. A first segment of a first data line and a first segment of a second data line are separated by a distance Wa. A first segment of a third data line and a first segment of a fourth data line are separated by a distance Wc. A second segment of the first data line and a second segment of the second data line are separated by a distance W1. A second segment of the third data line and a second segment of the fourth data line are separated by a distance W3. The distances Wa, Wc, W1 and W3 have a relationship (W1/Wa)?(W3/Wc).
    Type: Application
    Filed: June 14, 2020
    Publication date: December 31, 2020
    Inventors: Chia-Min Yeh, Hui-Min Huang, Hsieh-Li Chou, Cheng-Tso Chen, Yu-Chien Kao, Li-Wei Sung
  • Patent number: 10879203
    Abstract: A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Tse Chen, Hsiu-Jen Lin, Chih-Wei Lin, Cheng-Ting Chen, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20200402859
    Abstract: An apparatus includes a first source and a common drain and on opposite sides of a first gate surrounded by a first gate spacer, a second source and the common drain on opposite sides of a second gate surrounded by a second gate spacer, a first protection layer formed along a sidewall of the first gate spacer, wherein a top surface of the first protection layer has a first slope, a second protection layer formed along a sidewall of the second gate spacer, wherein a top surface of the second protection layer has a second slope, a lower drain contact between the first gate and the second gate and an upper drain contact over the lower drain contact and between the first gate and the second gate, wherein at least a portion of the upper drain contact is in contact with the first slope and the second slope.
    Type: Application
    Filed: September 3, 2020
    Publication date: December 24, 2020
    Inventors: Wan Hsuan Hsu, I-Hsiu Wang, Yean-Zhaw Chen, Cheng-Wei Chang, Yu Shih Wang, Hsin-Yan Lu, Yi-Wei Chiu
  • Publication number: 20200394803
    Abstract: An image identifying method is applied to a monitoring camera and a monitoring camera system and used to determine whether a target object is a leaving object or a missing object. The image identifying method includes acquiring a foreground region within a monitoring image corresponding to the target object, analyzing whether the target object inside the foreground region conforms to a variant feature, and comparing the foreground region with a reference image for determining the target object belongs to the leaving object or the missing object when the foreground region does not conform to the variant feature.
    Type: Application
    Filed: November 18, 2019
    Publication date: December 17, 2020
    Inventors: Cheng-Chieh Liu, Chia-Wei Chi, I-Lun Chen
  • Patent number: 10867862
    Abstract: A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsiung Yen, Ta-Chun Ma, Chien-Chang Su, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen
  • Patent number: 10867900
    Abstract: A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Hsien-Wei Chen, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Li-Han Hsu, Wei-Cheng Wu
  • Patent number: 10868136
    Abstract: Some embodiments of the present disclosure relate to a HEMT. The HEMT includes a heterojunction structure having a second III/V semiconductor layer arranged over a first III/V semiconductor layer. Source and drain regions are arranged over the substrate and spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. A first passivation layer is disposed about sidewalls of the gate structure and extending over an upper surface of the gate structure, wherein the first passivation layer is made of a III-V material. A second passivation layer overlies the first passivation layer and made of a material composition different from a material composition of the first passivation layer. The second passivation layer has a thickness greater than that of the first passivation layer.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
  • Patent number: 10861692
    Abstract: A method includes receiving a carrier with a plurality of wafers inside; supplying a purge gas to an inlet of the carrier; extracting an exhaust gas from an outlet of the carrier; and generating a health indicator of the carrier while performing the supplying of the purge gas and the extracting of the exhaust gas.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jen-Ti Wang, Chih-Wei Lin, Fu-Hsien Li, Yi-Ming Chen, Cheng-Ho Hung
  • Patent number: 10860769
    Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Katherine Chiang, Cheng Hsiao, Chang-Yu Huang, Juan Yi Chen, Ke-Wei Su, Chung-Kai Lin, Lester Chang, Min-Chie Jeng
  • Patent number: 10853552
    Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Lin Wu, Cheng-Cheng Kuo, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen, Yuan-Hsiang Lung, Yan-Tso Tsai
  • Patent number: 10854803
    Abstract: A manufacturing method of a light emitting device package structure is provided. The method includes following operations: (i) providing a circuit redistribution structure; (ii) providing a first substrate; (iii) forming a circuit layer structure over the first substrate, wherein the circuit layer structure includes a first circuit layer; (iv) before or after operation (iii), placing a light emitting device between the first substrate and the circuit layer structure or over the circuit layer structure, wherein the light emitting device is electrically connected with the first circuit layer; and (v) placing the circuit redistribution structure over the light emitting device, wherein the circuit redistribution structure includes a first redistribution layer, a second redistribution layer, and a chip, and the first redistribution layer includes a second circuit layer and a conductive contact that contacts the second circuit layer.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: December 1, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Pei-Wei Wang, Cheng-Ta Ko, Yu-Hua Chen, De-Shiang Liu, Tzyy-Jang Tseng
  • Patent number: 10854780
    Abstract: A light emitting device including a light emitting unit and a phosphor resin layer is provided. The light emitting unit has a top surface and a bottom surface opposite to each other. Each of the light emitting units includes two electrodes. The two electrodes are disposed on the bottom surface. The phosphor resin layer is disposed on the top surface of the light emitting unit. One side of the phosphor resin layer has a mark. One of the two electrodes is closer to the mark with respect to the other one of the two electrodes.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: December 1, 2020
    Assignee: Genesis Photonics Inc.
    Inventors: Cheng-Wei Hung, Chin-Hua Hung, Xun-Xain Zhan, Chuan-Yu Liu, Yun-Chu Chen, Yu-Feng Lin
  • Publication number: 20200371425
    Abstract: In a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. A resist pattern is formed by using a lithographic operation. The light blocking layer is patterned by using the resist pattern as an etching mask. The phase shift layer is patterned by using the patterned light blocking layer as an etching mask. A border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. The patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. A photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: Chun-Chieh TIEN, Cheng-Hsuen CHIANG, Chih-Ming CHEN, Cheng-Ming LIN, Yen-Wei HUANG, Hao-Ming CHANG, Kuo-Chin LIN, Kuan-Shien LEE
  • Patent number: 10847460
    Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shun Li Chen, Shih-Wei Peng, Tien-Lu Lin
  • Patent number: 10840965
    Abstract: A testing system includes: a bilinear polarized antenna for receiving and dividing a circularly polarized radio wave associating with a horizontal and a vertical polarization path of an object-to-be-tested into a first and a second high frequency signal; a phase retarder for delaying a phase of the first high frequency signal by 90 degrees to form a first high frequency signal with a phase delay of 90 degrees; a power splitter for receiving or synthesizing the first high frequency signal with the phase delay of 90 degrees and the second high frequency signal; and a high frequency signal transceiver for measuring power of the first high frequency signal with the phase delay of 90 degrees and the second high frequency signal and determining states of the horizontal and vertical polarization paths of the object-to-be-tested based on the power. Therefore, the testing system can speed up testing of the object-to-be-tested.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: November 17, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Bo-Siang Fang, Kuan-Ta Chen, Ying-Wei Lu, Chia-Chu Lai, Cheng-Tsai Hsieh
  • Publication number: 20200356508
    Abstract: A host-to-host chip includes: first and second ports coupled to first and second hosts respectively; and a host-to-host control circuit coupled to the first port and the second port. When the host-to-host chip is coupled to the second host, the host-to-host control circuit identifies whether the second host is an i-Phone or an Android smartphone. If the host-to-host control circuit identifies that the second host is an i-Phone smartphone, in response to a command from the host-to-host control circuit, the second host switches to host role from device role, and the host-to-host control circuit controls whether data is transmitted between the first host and the second host via a DMA path. If the host-to-host control circuit identifies that the second host is an Android smartphone, the host-to-host control circuit determines that data is transmitted between the first host and the second host in a pass-through mode.
    Type: Application
    Filed: May 5, 2020
    Publication date: November 12, 2020
    Applicant: PROLIFIC TECHNOLOGY INC.
    Inventors: Tien-Wei YU, Cheng-Sheng CHAN, Chiun-Shiu CHEN
  • Patent number: 10833030
    Abstract: A redistribution layer with a landing pad is formed over a substrate with one or more mesh holes extending through the landing pad. The mesh holes may be arranged in a circular shape, and a passivation layer may be formed over the landing pad and the mesh holes. An opening is formed through the passivation layer and an underbump metallization is formed in contact with an exposed portion of the landing pad and extends over the mesh holes. By utilizing the mesh holes, sidewall delamination and peeling that might otherwise occur may be reduced or eliminated.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Hsien-Wei Chen, Chen-Hua Yu, Tsung-Shu Lin, Wei-Cheng Wu
  • Patent number: 10823776
    Abstract: A testing fixture used in an antenna testing process is provided. A cover unit having a second antenna portion is arranged on a base unit configured for an electronic structure having a first antenna portion to be placed thereon. The cover unit includes a non-metal interposing portion configured for pressing the electronic structure to separate the second antenna portion from the first antenna portion. Therefore, when the antenna testing process is performed on the electronic structure, a metal shielding effect is avoided, and an over the air testing environment is provided.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: November 3, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Bo-Siang Fang, Cheng-Tsai Hsieh, Kuan-Ta Chen, Ying-Wei Lu