Patents by Inventor Cheng-wei Chen

Cheng-wei Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200083156
    Abstract: A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.
    Type: Application
    Filed: November 15, 2019
    Publication date: March 12, 2020
    Inventors: Cheng-Hsien Hsieh, Hsien-Wei Chen, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Li-Han Hsu, Wei-Cheng Wu
  • Publication number: 20200075563
    Abstract: Package structures and methods of forming them are described. In an embodiment, a package structure includes an integrated circuit die embedded in an encapsulant and a redistribution structure on the encapsulant. The redistribution structure includes a metallization layer distal from the encapsulant and the integrated circuit die, and a dielectric layer distal from the encapsulant and the integrated circuit die and on the metallization layer. The package structure also includes a first under metallization structure on the dielectric layer and a Surface Mount Device and/or Integrated Passive Device (“SMD/IPD”) attached to the first under metallization structure. The first under metallization structure includes first through fourth extending portions extending through first through fourth openings of the dielectric layer to first through fourth patterns of the metallization layer, respectively.
    Type: Application
    Filed: November 6, 2019
    Publication date: March 5, 2020
    Inventors: Cheng-Hsien Hsieh, Hsien-Wei Chen, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Wei-Cheng Wu
  • Publication number: 20200072886
    Abstract: A testing fixture used in an antenna testing process is provided. A cover unit having a second antenna portion is arranged on a base unit configured for an electronic structure having a first antenna portion to be placed thereon. The cover unit includes a non-metal interposing portion configured for pressing the electronic structure to separate the second antenna portion from the first antenna portion. Therefore, when the antenna testing process is performed on the electronic structure, a metal shielding effect is avoided, and an over the air testing environment is provided.
    Type: Application
    Filed: May 9, 2019
    Publication date: March 5, 2020
    Inventors: Bo-Siang Fang, Cheng-Tsai Hsieh, Kuan-Ta Chen, Ying-Wei Lu
  • Publication number: 20200075405
    Abstract: A method for reducing wiggling in a line includes forming a first patterning layer over a metal feature and depositing a first mask layer over the first patterning layer. The first mask layer is patterned to form a first set of one or more openings therein and then thinned. The pattern of the first mask layer is transferred to the first patterning layer to form a second set of one or more openings therein. The first patterning layer is etched to widen the second set of one or more openings. The first patterning layer may be comprised of silicon or an oxide material. The openings in the first patterning layer may be widened while a mask layer is over the first patterning layer.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 5, 2020
    Inventors: Kuan-Wei Huang, Cheng-Li Fan, Yu-Yu Chen
  • Publication number: 20200075729
    Abstract: A device is manufactured by etching a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.
    Type: Application
    Filed: June 17, 2019
    Publication date: March 5, 2020
    Inventors: Cheng-Hsiung Yen, Ta-Chun Ma, Chien-Chang Su, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen
  • Publication number: 20200062738
    Abstract: A compound for inhibiting BMI-1/MCL-1 having a structure of Formula (I), wherein the various groups are as described. A pharmaceutical composition for treating cancer includes an effective amount of a compound of Formula (I).
    Type: Application
    Filed: April 30, 2018
    Publication date: February 27, 2020
    Applicants: Development Center for Biotechnology, National Yang-Ming University
    Inventors: Cheng-Wen Wu, Erh-Hsuan Jiann Lin, Chi-Ying Huang, Jia-Ming Chang, Shih-Hsien Chuang, Hui-Jan Hsu, Wei-Wei Chen
  • Publication number: 20200060387
    Abstract: The present invention relates to a composition of a hot-melt adhesive film and a method for producing a shoe sole. The composition of the hot-melt adhesive film comprises a hot-melt adhesive material and an electromagnetic radiation absorbing material. The hot-melt adhesive material includes ethylene vinyl acetate and thermoplastic materials. The electromagnetic radiation absorbing material is uniformly dispersed in the hot-melt adhesive material. Energy of an electromagnetic radiation can be absorbed by the electromagnetic radiation absorbing material, thereby producing thermal energy, further increasing temperature and adhering property of the hot-melt adhesive film. Therefore, a midsole and an outsole of the shoe sole can be adhered by the hot-melt adhesive film. Further, the hot-melt adhesive film is made from recyclable materials. Therefore, the hot-melt adhesive film is fully recyclable.
    Type: Application
    Filed: August 25, 2019
    Publication date: February 27, 2020
    Inventors: Chuh-Yung CHEN, Cheng-Wei HUANG, Meng-Heng WU, Chao-Yu LAI, Yu-Ning SHU, Chen-Chien WANG
  • Patent number: 10566261
    Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: February 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
  • Publication number: 20200046450
    Abstract: A system for imparting motion of an object includes: (1) at least one first hydrostatic actuator; (2) a hydraulic transmission conduit; and (3) at least one second hydrostatic actuator. The first hydrostatic actuator is connected to the second hydrostatic actuator via the hydraulic transmission conduit, such that an input displacement applied to the first hydrostatic actuator is transmitted via the hydraulic transmission conduit to the second hydrostatic actuator to impart motion of the object.
    Type: Application
    Filed: February 20, 2018
    Publication date: February 13, 2020
    Inventors: Tsu-Chin TSAO, James M. SIMONELLI, Holden H. WU, Samantha MIKAIEL, Yu-Hsiu LEE, Cheng-Wei CHEN, Kyung Hyun SUNG, David S. LU
  • Publication number: 20200052133
    Abstract: A semiconductor device includes channel layers disposed over a substrate, a source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the channel layers, and a gate electrode layer disposed on the gate dielectric layer and wrapping each of the channel layers. Each of the channel layers includes a semiconductor wire made of a core region, and one or more shell regions. The core region has an approximately square-shape cross section and a first shell of the one or more shells forms a first shell region of an approximately rhombus-shape cross section around the core region and is connected to an adjacent first shell region corresponding to a neighboring semiconductor wire.
    Type: Application
    Filed: October 18, 2019
    Publication date: February 13, 2020
    Inventors: I-Sheng CHEN, Szu-Wei HUANG, Hung-Li CHIANG, Cheng-Hsien WU, Chih Chieh YEH
  • Publication number: 20200040900
    Abstract: A thin cooling fan includes a fan shell, a motor, a plurality of blades, and a PCB. The fan shell comprises a base plate and a shell cover which cover to each other to form an inner space. The base plate has a first surface facing toward the inner space and a second surface having a receiving space and opposite to the first surface. The motor is combined in the inner space. The blades are disposed in the inner space and rotated by the motor. The PCB is disposed in the receiving space and flush with the second surface. Thus, the whole thickness of the cooling fan is reduced and the flow channel design in the inner space is not affected.
    Type: Application
    Filed: October 10, 2019
    Publication date: February 6, 2020
    Inventors: Cheng-Wei CHEN, Hsiang-Jung HUANG
  • Publication number: 20200045777
    Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.
    Type: Application
    Filed: October 11, 2019
    Publication date: February 6, 2020
    Inventors: Ming-Da Cheng, Hsiu-Jen Lin, Cheng-Ting Chen, Wei-Yu Chen, Chien-Wei Lee, Chung-Shi Liu
  • Publication number: 20200035875
    Abstract: A light-emitting device including at least one light-emitting unit, a wavelength conversion adhesive layer, and a reflective protecting element is provided. The light-emitting unit has an upper surface and a lower surface opposite to each other. The light-emitting unit includes two electrode pads, and the two electrode pads are located on the lower surface. The wavelength conversion adhesive layer is disposed on the upper surface. The wavelength conversion adhesive layer includes a low-concentration fluorescent layer and a high-concentration fluorescent layer. The high-concentration fluorescent layer is located between the low-concentration fluorescent layer and the light-emitting unit. The width of the high-concentration fluorescent layer is WH. The width of the low-concentration fluorescent layer is WL. The width of the light-emitting unit is WE. The light-emitting device further satisfies the following inequalities: WE<WL, WH<WL and 0.8<WH/WE?1.2.
    Type: Application
    Filed: October 7, 2019
    Publication date: January 30, 2020
    Applicant: Genesis Photonics Inc.
    Inventors: Cheng-Wei Hung, Long-Chi Tu, Jui-Fu Chang, Chun-Ming Tseng, Yun-Chu Chen
  • Publication number: 20200035680
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.
    Type: Application
    Filed: October 6, 2019
    Publication date: January 30, 2020
    Inventors: Yen-Wei Tung, Jen-Yu Wang, Cheng-Tung Huang, Yan-Jou Chen
  • Publication number: 20200027691
    Abstract: An electron microscope specimen includes a first electron-transport layer, a second electron-transport layer, a spacer layer, and a carrier layer. The second electron-transport layer has a first opening, a second opening, and a viewing area, wherein the viewing area is between the first opening and the second opening. The spacer layer is sandwiched between the first electron-transport layer and the second electron-transport layer, and the spacer layer has an accommodating space communicating with the first opening and the second opening. The carrier layer is disposed on the second electron-transport layer, and has a viewing window, a first injection hole, and a second injection hole, wherein the viewing window is substantially aligned with the viewing area and the accommodating space, and the first injection hole and the second injection hole respectively communicate with the first opening and the second opening.
    Type: Application
    Filed: June 4, 2019
    Publication date: January 23, 2020
    Inventors: Wen-Wei WU, Wei-Huan TSAI, Jui-Yuan CHEN, Cheng-Lun HSIN
  • Publication number: 20200020625
    Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shun Li Chen, Shih-Wei Peng, Tien-Lu Lin
  • Patent number: 10529863
    Abstract: Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile, by the thermal hydrogen treatment.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ta Wu, Cheng-Wei Chen, Shiu-Ko Jangjian, Ting-Chun Wang
  • Publication number: 20200000350
    Abstract: The present invention provides a dynamic measurement device with a blood pressure determination function, comprising: a heartbeat sensing module disposed on the chest area of a user wherein the heartbeat sensing module comprising a heart sound sensor for obtaining heartbeat signals; a pulse sensing module disposed on a limb area of the user, the pulse sensing module comprising a pulse wave sensor for obtaining pulse signals; and a data calculating module for calculating a mean arterial pressure and a value of systolic blood pressure and diastolic blood pressure based on the heartbeat signals and pulse signals. In addition to dynamically monitoring the blood pressure of a user for 24 hours, the present invention can dynamically monitor the heart sounds of the user for 24 hours individually in order to monitor user's physical condition. Therefore, the present invention has important medical meanings.
    Type: Application
    Filed: November 30, 2017
    Publication date: January 2, 2020
    Inventors: Shiming LIN, Shih-Wei CHIANG, Cheng-Yan GUO, Tai-Cun LIN, Wei-Chih HUANG, Chun-Nan CHEN, Ya-Ting CHANG
  • Publication number: 20200006610
    Abstract: A light emitting device package structure includes a substrate, a circuit layer structure, a light emitting device, a first redistribution layer, a conductive connector, a second redistribution layer, and a chip. The circuit layer structure is disposed over the substrate, and the circuit layer structure includes a first circuit layer. The light emitting device is disposed over the circuit layer structure and is electrically connected with the first circuit layer. The first redistribution layer is disposed over the light emitting device and includes a second circuit layer and a conductive contact contacting the second circuit layer. The conductive connector connects the first circuit layer and the second circuit layer. The second redistribution layer is disposed over the first redistribution layer and includes a third circuit layer contacting the conductive contact. The chip is disposed over the second redistribution layer and is electrically connected with the third circuit layer.
    Type: Application
    Filed: September 25, 2018
    Publication date: January 2, 2020
    Inventors: Pei-Wei WANG, Cheng-Ta KO, Yu-Hua CHEN, De-Shiang LIU, Tzyy-Jang TSENG
  • Publication number: 20200006191
    Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.
    Type: Application
    Filed: September 13, 2019
    Publication date: January 2, 2020
    Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu