Patents by Inventor Cheng-Wei Cheng

Cheng-Wei Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9711617
    Abstract: A method of making a dual isolation fin comprises applying a mask to a substrate and etching the exposed areas of the substrate to form a mandrel; forming a dielectric layer on the surface of the substrate and adjacent to the mandrel; forming a first epitaxially formed material on the exposed portions of the mandrel; forming a second epitaxially formed material on the first epitaxially formed material; forming a first isolation layer on the dielectric layer and adjacent to the second epitaxially formed material; removing the mask and mandrel after forming the first isolation layer; removing the first epitaxially formed material after removing the mask and mandrel; and forming a second isolation layer.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: July 18, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Sanghoon Lee, Effendi Leobandung
  • Patent number: 9704958
    Abstract: An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second III-V semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: July 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Edward William Kiewra, Amlan Majumdar, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Publication number: 20170179288
    Abstract: A semiconductor device comprises a first layer of a substrate arranged on a second layer of the substrate the second layer of the substrate including a doped III-V semiconductor material barrier layer, a gate stack arranged on a channel region of the first layer of a substrate, a spacer arranged adjacent to the gate stack on the first layer of the substrate, an undoped epitaxially grown III-V semiconductor material region arranged on the second layer of the substrate, and an epitaxially grown source/drain region arranged on the undoped epitaxially grown III-V semiconductor material region, and a portion of the first layer of the substrate.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Inventors: Cheng-Wei Cheng, Pranita Kerber, Amlan Majumdar, Yanning Sun
  • Publication number: 20170179237
    Abstract: An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer.
    Type: Application
    Filed: February 27, 2017
    Publication date: June 22, 2017
    Inventors: CHENG-WEI CHENG, EDWARD WILLIAM KIEWRA, AMLAN MAJUMDAR, DEVENDRA K. SADANA, KUEN-TING SHIU, YANNING SUN
  • Publication number: 20170179232
    Abstract: A method for forming a semiconductor device comprising forming a sacrificial gate stack on a channel region of first layer of a substrate, forming a spacer adjacent to the sacrificial gate stack, forming a raised source/drain region on the first layer of the substrate adjacent to the spacer, forming a dielectric layer over the raised source/drain region, removing the sacrificial gate stack to expose the channel region of the first layer of the substrate, and implanting dopants in a second layer of the substrate to form an implant region in the second layer below the channel region of the first layer of the substrate, where the first layer of the substrate is arranged on the second layer of the substrate.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Inventors: Cheng-Wei Cheng, Pranita Kerber, Amlan Majumdar, Yanning Sun
  • Publication number: 20170179238
    Abstract: An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Inventors: CHENG-WEI CHENG, EDWARD WILLIAM KIEWRA, AMLAN MAJUMDAR, DEVENDRA K. SADANA, KUEN-TING SHIU, YANNING SUN
  • Publication number: 20170170297
    Abstract: A method of making a dual isolation fin comprises applying a mask to a substrate and etching the exposed areas of the substrate to form a mandrel; forming a dielectric layer on the surface of the substrate and adjacent to the mandrel; forming a first epitaxially formed material on the exposed portions of the mandrel; forming a second epitaxially formed material on the first epitaxially formed material; forming a first isolation layer on the dielectric layer and adjacent to the second epitaxially formed material; removing the mask and mandrel after forming the first isolation layer; removing the first epitaxially formed material after removing the mask and mandrel; and forming a second isolation layer.
    Type: Application
    Filed: December 9, 2015
    Publication date: June 15, 2017
    Inventors: CHENG-WEI CHENG, SANGHOON LEE, EFFENDI LEOBANDUNG
  • Publication number: 20170162387
    Abstract: A method of forming a semiconductor device is provided. The method includes depositing an aluminum-base interlayer on a silicon substrate, the aluminum-base interlayer having a thickness of less than about 100 nanometers; and growing a III-V compound material on the aluminum-base interlayer. The aluminum-base interlayer deposited directly on silicon allows for continuous and planar growth of III-V compound materials on the interlayer, which facilitates the manufacture of high quality electronic devices.
    Type: Application
    Filed: June 9, 2016
    Publication date: June 8, 2017
    Inventors: CHENG-WEI CHENG, SANGHOON LEE, KUEN-TING SHIU
  • Publication number: 20170154783
    Abstract: A method for performing epitaxial lift-off allowing reuse of a III-V substrate to grow III-V devices is presented. A sample is received comprising a growth substrate with a top surface, a sacrificial layer on the top surface, and a device layer on the sacrificial layer. This substrate is supported inside a container and the container is filled with a wet etchant such that the wet etchant progressively etches away the sacrificial layer and the device layer lifts away from the growth substrate. While filling the container with the wet etchant, the sample is supported in the container such that the top surface of the growth substrate is non-parallel with an uppermost surface of the wet etchant. Performed in this manner, the lift-off process requires little individual setup of the sample, and is capable of batch processing and high throughput.
    Type: Application
    Filed: February 13, 2017
    Publication date: June 1, 2017
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Leathen Shi, Kuen-Ting Shiu
  • Publication number: 20170140919
    Abstract: A heteroepitaxially grown structure includes a substrate and a mask including a high aspect ratio trench formed on the substrate. A cavity is formed in the substrate having a shape with one or more surfaces and including a resistive neck region at an opening to the trench. A heteroepitaxially grown material is formed on the substrate and includes a first region in or near the cavity and a second region outside the first region wherein the second region contains fewer defects than the first region.
    Type: Application
    Filed: December 30, 2016
    Publication date: May 18, 2017
    Inventors: Cheng-Wei Cheng, David L. Rath, Devendra K. Sadana, Kuen-Ting Shiu, Brent A. Wacaser
  • Patent number: 9653308
    Abstract: A method for performing epitaxial lift-off allowing reuse of a III-V substrate to grow III-V devices is presented. A sample is received comprising a growth substrate with a top surface, a sacrificial layer on the top surface, and a device layer on the sacrificial layer. This substrate is supported inside a container and the container is filled with a wet etchant such that the wet etchant progressively etches away the sacrificial layer and the device layer lifts away from the growth substrate. While filling the container with the wet etchant, the sample is supported in the container such that the top surface of the growth substrate is non-parallel with an uppermost surface of the wet etchant. Performed in this manner, the lift-off process requires little individual setup of the sample, and is capable of batch processing and high throughput.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: May 16, 2017
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Leathen Shi, Kuen-Ting Shiu
  • Publication number: 20170125970
    Abstract: A semiconductor device including a substrate structure including a semiconductor material layer that is present directly on a buried dielectric layer in a first portion of the substrate structure and an isolation dielectric material that is present directly on the buried dielectric layer in a second portion of the substrate structure. The semiconductor device further includes a III-V optoelectronic device that is present in direct contact with the isolation dielectric material in a first region of the second portion of the substrate structure. A dielectric wave guide is present in direct contact with the isolation dielectric material in a second region of the second portion of the substrate structure.
    Type: Application
    Filed: January 11, 2017
    Publication date: May 4, 2017
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Publication number: 20170125445
    Abstract: A structure includes an off axis Si substrate with an overlying s-Si1?xGe, layer and a BOX between the off-axis Si substrate and the s-Si1?xGex layer. The structure further includes pFET fins formed in the s-Si1?xGex layer and a trench formed through the s-Si1?xGe, layer, the BOX and partially into the off-axis Si substrate. The trench contains a buffer layer in contact with the off-axis Si substrate, a first Group III-V layer disposed on the buffer layer, a semi-insulating Group III-V layer disposed on the first Group III-V layer and a second Group III-V layer disposed on the semi-insulating Group III-V layer, as well as nFET fins formed in the second Group III-V layer. The s-Si1?xGex layer has a value of x that results from a condensation process that merges an initial s-Si1?xGex layer with an initial underlying on-axis <100> Si layer. A method to fabricate the structure is also disclosed.
    Type: Application
    Filed: January 10, 2017
    Publication date: May 4, 2017
    Inventors: Cheng-Wei Cheng, Pouya Hashemi, Effendi Leobandung, Alexander Reznicek
  • Patent number: 9627482
    Abstract: A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: April 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Pranita Kerber, Young-Hee Kim, Effendi Leobandung, Yanning Sun
  • Publication number: 20170104012
    Abstract: A structure includes an off-axis Si substrate with an overlying s-Si1-xGex layer and a BOX between the off-axis Si substrate and the s-Si1-xGex layer. The structure further includes pFET fins formed in the s-Si1-xGex layer and a trench formed through the s-Si1-xGex layer, the BOX and partially into the off-axis Si substrate. The trench contains a buffer layer in contact with the off-axis Si substrate, a first Group III-V layer disposed on the buffer layer, a semi-insulating Group III-V layer disposed on the first Group III-V layer and a second Group III-V layer disposed on the semi-insulating Group III-V layer, as well as nFET fins formed in the second Group III-V layer. The s-Si1-xGex layer has a value of x that results from a condensation process that merges an initial s-Si1-xGex layer with an initial underlying on-axis <100> Si layer. A method to fabricate the structure is also disclosed.
    Type: Application
    Filed: October 9, 2015
    Publication date: April 13, 2017
    Inventors: Cheng-Wei Cheng, Pouya Hashemi, Effendi Leobandung, Alexander Reznicek
  • Publication number: 20170092722
    Abstract: A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source comprising III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer comprising silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer comprising transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer comprising transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain.
    Type: Application
    Filed: April 22, 2016
    Publication date: March 30, 2017
    Inventors: Kevin K. Chan, Cheng-Wei Cheng, Jack Oon Chu, Yanning Sun, Jeng-Bang Yau
  • Publication number: 20170092727
    Abstract: A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source comprising III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer comprising silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer comprising transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer comprising transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 30, 2017
    Inventors: Kevin K. Chan, Cheng-Wei Cheng, Jack Oon Chu, Yanning Sun, Jeng-Bang Yau
  • Publication number: 20170092763
    Abstract: A semiconductor structure containing a high mobility semiconductor channel material, i.e., a III-V semiconductor material, and asymmetrical source/drain regions located on the sidewalls of the high mobility semiconductor channel material is provided. The asymmetrical source/drain regions can aid in improving performance of the resultant device. The source region contains a source-side epitaxial doped semiconductor material, while the drain region contains a drain-side epitaxial doped semiconductor material and an underlying portion of the high mobility semiconductor channel material.
    Type: Application
    Filed: December 13, 2016
    Publication date: March 30, 2017
    Inventors: Cheng-Wei Cheng, Pranita Kerber, Effendi Leobandung, Amlan Majumdar, Renee T. Mo, Yanning Sun
  • Patent number: 9608160
    Abstract: After forming patterned dielectric material structures over a (100) silicon substrate, portions of the silicon substrate that are not covered by the patterned dielectric material structures are removed to provide a plurality of openings within the silicon substrate. Each opening exposes a surface of the silicon substrate having a (111) crystalline plane. A buffer layer is then formed on the exposed surfaces of the patterned dielectric material structures and the silicon substrate. A dual phase Group III nitride structure including a cubic phase region is formed filling a space between each neighboring pair of the patterned dielectric material structures and one of the openings located beneath the space. Finally, at least one Group III nitride layer is epitaxially deposited over the cubic phase region of the dual phase Group III nitride structure.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: March 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Can Bayram, Cheng-Wei Cheng, Tayfun Gokmen, Ning Li, John A. Ott, Devendra K. Sadana, Kuen-Ting Shiu
  • Publication number: 20170075062
    Abstract: An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate. The interlevel dielectric layer is present over the first and second semiconductor devices. An optical interconnect is positioned over the second portion of the semiconductor substrate. At least one material layer of the optical interconnect includes an epitaxial material that is in direct contact with a seed surface within the second portion of the substrate through a via extending through the least one interlevel dielectric layer.
    Type: Application
    Filed: November 29, 2016
    Publication date: March 16, 2017
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu