Patents by Inventor Cheng Youn Lu

Cheng Youn Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6909731
    Abstract: An automatic closed loop power control system is described for simultaneously adjusting an output power and an extinction ratio P1/P0 of a laser diode in order to maintain a desired average output power and a desired extinction ratio. The bias current component of a laser diode drive current is adjusted to compensate for changes in the average output power caused by ambient characteristics such as temperature and aging. Simultaneously, a modulation current component of the laser diode drive current is adjusted to maintain an extinction ratio of the laser diode output signal. The bias current and modulation current adjustments are based on the second order statistics of an average output power of the laser diode and a variance in the power output of the laser diode.
    Type: Grant
    Filed: January 22, 2004
    Date of Patent: June 21, 2005
    Inventor: Cheng Youn Lu
  • Publication number: 20040165622
    Abstract: An automatic closed loop power control system is described for simultaneously adjusting an output power and an extinction ratio P1/P0 of a laser diode in order to maintain a desired average output power and a desired extinction ratio. The bias current component of a laser diode drive current is adjusted to compensate for changes in the average output power caused by ambient characteristics such as temperature and aging. Simultaneously, a modulation current component of the laser diode drive current is adjusted to maintain an extinction ratio of the laser diode output signal. The bias current and modulation current adjustments are based on the second order statistics of an average output power of the laser diode and a variance in the power output of the laser diode.
    Type: Application
    Filed: January 22, 2004
    Publication date: August 26, 2004
    Inventor: Cheng Youn Lu
  • Patent number: 6760574
    Abstract: A method for detecting an input signal at a transceiver of a communication system is disclosed, and includes compensating for timing misalignment between when the receipt of the input signal was indicated and when the input signal actually arrived. A signal detector for detecting an input signal and adapted to compensate for timing misalignment is also disclosed.
    Type: Grant
    Filed: April 17, 2001
    Date of Patent: July 6, 2004
    Assignee: Centillium Communications, Inc.
    Inventors: Cheng-Youn Lu, Judith Wang
  • Patent number: 6516036
    Abstract: Method and apparatus for determining the correct set of samples to retain in applying a decimation process. The present method provides an automatic approach to determine the timing phase of the desired samples to decimate the oversampled input signal (data sequence), thereby producing the underlying data signal.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: February 4, 2003
    Assignees: Sarnoff Corporation, Motorola, Inc.
    Inventors: Cheng-Youn Lu, Randall Bret Perlow, Charles Reed, Jr.
  • Patent number: 6128357
    Abstract: An adaptable, variable rate symbol timing recovery system for a digital sal receiver comprises an analog to digital (A-D) signal converter having analog signal input and digital data signal output terminals. A source of selectable, substantially fixed rate, data sampling clock signals is coupled to the A-D signal converter for sampling a signal received at the input at a predetermined, substantially fixed clock rate, depending on data rate and modulation of the received signal. A digital signal processing loop is coupled to the digital data signal output terminal for adjustably producing interdependent signals in synchronism with the data signals at the output terminal which are asynchronous with respect to the fixed rate clock signals. A Controller is provided for selectively configuring the data sampling clock signal source and the digital signal processing loop according to the data rate and modulation characteristics of the received signal.
    Type: Grant
    Filed: December 24, 1997
    Date of Patent: October 3, 2000
    Assignee: Mitsubishi Electric Information Technology Center America, Inc (ITA)
    Inventors: Cheng-Youn Lu, Jay Bao, Tommy C. Poon
  • Patent number: 5777910
    Abstract: A sparse digital adaptive equalizer including forward and feedback Finite Impulse Response (FIR) filters exhibits improved Least Mean Square operation. A switch assigns one of several multipliers of each filter to any one of the tap locations of that filter. Each multiplier is initially assigned to a preselected tap location with a predetermined weighting coefficient. After completing successive time cycles having a duration equal to a given number of data sample periods, for each filter there is determined (a) a first group of coefficients associated with multipliers then assigned to non-zero value tap locations, and (b) a second group of coefficients associated with multipliers then assigned to zero valued locations. Multipliers associated with first group coefficients during a just-completed time cycle retain their tap locations during the next time cycle.
    Type: Grant
    Filed: November 19, 1996
    Date of Patent: July 7, 1998
    Assignee: Thomson multimedia S.A.
    Inventor: Cheng-Youn Lu
  • Patent number: 5528195
    Abstract: A quadrature demodulator for demodulating an input signal which includes respective data signals modulating in-phase and quadrature carriers. The demodulator includes a voltage controlled oscillator responsive to a control signal for generating an oscillatory signal. A demodulator, coupled to receive the oscillatory signal from the voltage controlled oscillator and the input signal, provides the in-phase and quadrature components of the input signal. Phase comparison circuitry, responsive to the in-phase and quadrature components of the input signal generates a phase error signal. The phase error signal represents the difference, in phase and magnitude, between a vector defined by the in-phase and quadrature components of the input signal and reference vectors. Filter circuitry, responsive to the phase error signal, generates a control signal for the voltage controlled oscillator.
    Type: Grant
    Filed: May 9, 1995
    Date of Patent: June 18, 1996
    Assignee: Panasonic Technologies, Inc.
    Inventors: Cheng-Youn Lu, Robert S. Burroughs