Patents by Inventor Chern-Yow Hsu

Chern-Yow Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220285438
    Abstract: The present disclosure provides a semiconductor structure, and a method for fabricating a semiconductor structure, the method includes forming a bottom electrode, forming a magnetic tunneling junction (MTJ) layer over the bottom electrode, wherein the MTJ layer includes a first material, forming a top electrode over the MTJ layer, forming a first dielectric layer over the top electrode and the MTJ layer, and patterning the MTJ layer to form an MTJ, thereby generating residue over an outer sidewall of the first dielectric layer, wherein the residue comprises the first material, and the residue is apart from the bottom electrode, forming a second dielectric layer over the first dielectric layer to encapsulate the residue, and forming an insulation layer surrounding the second dielectric layer.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 8, 2022
    Inventor: CHERN-YOW HSU
  • Patent number: 11430956
    Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.
    Type: Grant
    Filed: September 21, 2019
    Date of Patent: August 30, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming Chyi Liu, Yuan-Tai Tseng, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
  • Publication number: 20220216267
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a memory region, the memory region includes a first metal line, a magnetic tunneling junction (MTJ) over the first metal line, a cap. wherein at least a portion of the cap is above the MTJ, a first stop layer above the cap, and a first metal via being disposed over the MTJ and in direct contact with the first stop layer, and a logic region adjacent to the memory region, the logic region includes a second metal line, a third metal line over the second metal line, a second stop layer being disposed over the third metal line, and a second metal via over the third metal line.
    Type: Application
    Filed: March 21, 2022
    Publication date: July 7, 2022
    Inventors: CHERN-YOW HSU, YUAN-TAI TSENG, SHIH-CHANG LIU
  • Patent number: 11367832
    Abstract: A method of making a magnetoresistive random access memory (MRAM) device includes forming a bottom conductive layer. The method includes forming an anti-ferromagnetic layer over the bottom conductive layer and forming a tunnel layer over the anti-ferromagnetic layer. The method includes forming a free magnetic layer, having a magnetic moment aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer, wherein the anti-ferromagnetic layer, the tunnel layer and the free magnetic layer are part of a magnetic tunnel junction (MTJ) unit. The method includes forming a top conductive layer over the free magnetic layer. The method includes performing at least one lithographic process to remove portions of the bottom conductive layer, the MTJ unit and the top conductive layer that is uncovered by a photoresist layer. The method includes removing a portion of a sidewall of the MTJ unit.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: June 21, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 11362265
    Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Fu-Ting Sung, Chung-Chiang Min, Yuan-Tai Tseng, Chern-Yow Hsu, Shih-Chang Liu
  • Publication number: 20220181312
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first dielectric structure having first inner sidewalls over an interlayer dielectric (ILD) structure. A second dielectric structure is over the first dielectric structure, where the first inner sidewalls are between second inner sidewalls of the second dielectric structure. A sidewall barrier structure is over the first dielectric structure and extends vertically along the second inner sidewalls. A lower bumping structure is between the second inner sidewalls and extends vertically along the first inner sidewalls and vertically along third inner sidewalls of the sidewall barrier structure. An upper bumping structure is over both the lower bumping structure and the sidewall barrier structure and between the second inner sidewalls, where an uppermost point of the upper bumping structure is at or below an uppermost point of the second dielectric structure.
    Type: Application
    Filed: February 24, 2022
    Publication date: June 9, 2022
    Inventors: Ching-Sheng Chu, Chern-Yow Hsu
  • Patent number: 11342378
    Abstract: The present disclosure provides a semiconductor structure, including a magnetic tunneling junction (MTJ), a top electrode over a top surface of the MTJ, a first dielectric layer surrounding the top electrode, wherein a bottom surface of the first dielectric contacts with a top surface of the MTJ, and a second dielectric layer surrounding the first dielectric layer and the MTJ.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: May 24, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chern-Yow Hsu
  • Publication number: 20220157751
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a bond pad disposed over a substrate and a passivation structure disposed over the substrate and the bond pad. The passivation structure has one or more sidewalls directly over the bond pad. A protective layer is disposed directly between the passivation structure and the bond pad. The passivation structure extends from directly over the protective layer to laterally past a sidewall of the protective layer that faces a central region of the bond pad.
    Type: Application
    Filed: February 1, 2022
    Publication date: May 19, 2022
    Inventors: Tzu-Hsuan Yeh, Chern-Yow Hsu
  • Publication number: 20220131072
    Abstract: A memory device includes a bottom electrode, a magnetic tunnel junction (MTJ) structure, an inner spacer, and an outer spacer. The MTJ structure is over the bottom electrode. The bottom electrode has a top surface extending past opposite sidewalls of the MTJ structure. The inner spacer contacts the top surface of the bottom electrode and one of the opposite sidewalls of the MTJ structure. The outer spacer contacts an outer sidewall of the inner spacer. The outer spacer protrudes from a top surface of the inner spacer by a step height.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-Ting SUNG, Chern-Yow HSU, Shih-Chang LIU
  • Publication number: 20220123203
    Abstract: A memory cell structure including a dielectric cap layer disposed over a substrate and a first dielectric layer disposed over the dielectric cap layer. The memory cell structure may further include a buffer layer disposed over the first dielectric layer, a connection via structure embedded in the buffer layer, the first dielectric layer, and the dielectric cap layer. The memory cell structure may further include may further include a bottom electrode disposed on the connection via structure and the buffer layer, and a magnetic tunnel junction (MTJ) memory cell including one or more MTJ layers disposed on the bottom electrode.
    Type: Application
    Filed: October 19, 2020
    Publication date: April 21, 2022
    Inventor: Chern-Yow HSU
  • Publication number: 20220115349
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a bond bump disposed on an upper surface of an upper conductive structure. The upper conductive structure overlies a substrate. A buffer layer is disposed along the upper surface of the upper conductive structure. The bond bump comprises a sidewall having a straight sidewall segment overlying a curved sidewall segment.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventors: Ching-Sheng Chu, Chern-Yow Hsu
  • Patent number: 11302663
    Abstract: A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Chang, Chern-Yow Hsu, Cheng-Yuan Tsai, Kong-Beng Thei
  • Publication number: 20220069204
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory cell. In some embodiments, a memory film is deposited over a substrate and comprises a bottom electrode layer, a top electrode layer, and a data storage film between the top and bottom electrode layers. A hard mask film is deposited over the memory film and comprises a conductive hard mask layer. The top electrode layer and the hard mask film are patterned to respectively form a top electrode and a hard mask over the top electrode. A trimming process is performed to decrease a sidewall angle between a sidewall of the hard mask and a bottom surface of the hard mask. An etch is performed into the data storage film with the hard mask in place after the trimming process to form a data storage structure underlying the top electrode.
    Type: Application
    Filed: October 23, 2020
    Publication date: March 3, 2022
    Inventors: Min-Yung Ko, Chern-Yow Hsu, Chang-Ming Wu, Shih-Chang Liu
  • Patent number: 11264368
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first dielectric structure having first inner sidewalls over an interlayer dielectric (ILD) structure. A second dielectric structure is over the first dielectric structure, where the first inner sidewalls are between second inner sidewalls of the second dielectric structure. A sidewall barrier structure is over the first dielectric structure and extends vertically along the second inner sidewalls. A lower bumping structure is between the second inner sidewalls and extends vertically along the first inner sidewalls and vertically along third inner sidewalls of the sidewall barrier structure. An upper bumping structure is over both the lower bumping structure and the sidewall barrier structure and between the second inner sidewalls, where an uppermost point of the upper bumping structure is at or below an uppermost point of the second dielectric structure.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Sheng Chu, Chern-Yow Hsu
  • Patent number: 11258007
    Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hang Huang, Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 11244914
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a bond pad layer onto a dielectric structure formed over a substrate. The dielectric structure surrounds a plurality of interconnect layers. A protective layer is formed onto the bond pad layer, and the bond pad layer and the protective layer are patterned to define a bond pad covered by the protective layer. One or more upper passivation layers are formed over the protective layer. A dry etching process is performed to form an opening extending through the one or more upper passivation layers to the protective layer. A wet etching process is performed to remove a part of the protective layer and expose an upper surface of the bond pad.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: February 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Hsuan Yeh, Chern-Yow Hsu
  • Patent number: 11227993
    Abstract: A device includes a first conductive via plug, a first electrode, a storage element, a second electrode, a spacer, a barrier structure, a first dielectric layer. The first electrode is over the first conductive via plug. The storage element is over the first electrode. The second electrode is over the storage element. The spacer has a bottom portion extending along a top surface of the first electrode and a standing portion extending from the bottom portion and along a sidewall of the second electrode. The barrier structure extends from the bottom portion of the spacer and along a sidewall of the standing portion of the spacer. The first dielectric layer is substantially conformally over the spacer and the barrier structure.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: January 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu
  • Patent number: 11222896
    Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor includes a first electrode over at least one dielectric layer over the active region. The first electrode surrounds an open space within the capacitor. The first electrode has a non-linear first electrode sidewall.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chern-Yow Hsu, Chen-Jong Wang, Chia-Shiung Tsai, Ming Chyi Liu, Shih-Chang Liu, Xiaomeng Chen
  • Patent number: 11211352
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device structure including a bump structure overlying a bond pad. The bond pad is disposed over a semiconductor substrate. An etch stop layer overlies the bond pad. A buffer layer is disposed over the bond pad and separates the etch stop layer and the bond pad. The bump structure includes a base portion contacting an upper surface of the bond pad and an upper portion extending through the etch stop layer and the buffer layer. The base portion of the bump structure has a first width or diameter and the upper portion of the bump structure has a second width or diameter. The first width or diameter being greater than the second width or diameter.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Sheng Chu, Chern-Yow Hsu
  • Publication number: 20210351142
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a bond pad layer onto a dielectric structure formed over a substrate. The dielectric structure surrounds a plurality of interconnect layers. A protective layer is formed onto the bond pad layer, and the bond pad layer and the protective layer are patterned to define a bond pad covered by the protective layer. One or more upper passivation layers are formed over the protective layer. A dry etching process is performed to form an opening extending through the one or more upper passivation layers to the protective layer. A wet etching process is performed to remove a part of the protective layer and expose an upper surface of the bond pad.
    Type: Application
    Filed: May 5, 2020
    Publication date: November 11, 2021
    Inventors: Tzu-Hsuan Yeh, Chern-Yow Hsu