Abstract: The invention is directed to a memory controller for use with memory having varying timing characteristics. In particular, the timing characteristics of the various memory devices are determined and used to generate timing signals commensurate with each particular memory device.

Abstract: A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.

Abstract: A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.

Abstract: Timing calculator means in a computer system are used to adaptively generate an appropriate access signal, to one of a plurality of memory types, based on first and second timing control values, wherein the first timing control value represents information specific to and limited to the start of a memory operation and wherein the second timing control value represents information representing other timing events. That is, the state machine of the present invention requires a distinct starting control value, separate from other timing values, for calculation of appropriate memory access parameters.

Abstract: A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.

Abstract: A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.

Abstract: A processing unit couples to a system bus in common with a peer processor, a main memory, in addition to other units, and includes a microprocessor which tightly couples to a local memory also accessible from such bus. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which is coupled to the microprocessor and the system bus. The EEPROM unit stores in first and second separate regions, both of which occupy the same address space normally allocated for storing the microprocessor's boot code, on-board diagnostic (OBD) routines and operating system boot routines, respectively. EEPROM control circuits at power-up, condition the EEPROM unit to address the first region for executing OBD routines to verify that the processing unit is operating properly, including the ability to properly issue commands to units connected to the system bus.

Abstract: A data processing system includes a system management unit, a number of central subsystems, a main memory and a number of peripheral subsystems all coupled in common to a system bus. Any subsystem may generate a command which includes a first field specifying a destination subsystem, a second field specifying the operation the destination subsystem is to perform. If a response is required, the subsystem generating the initial command may specify a third subsystem for receiving the response command.

Abstract: A memory system coupled to a local bus of a microprocessor includes at least a pair of dynamic random access memories (DRAMs) and includes circuits for storing the first address of an address sequence at the beginning of each burst operation and uses predetermined bits to generate any one of a set of address sequences as a function of the states of these bits. A first predetermined address bit is used to select different sequences of addressed readout data words to be transferred by the pair of DRAMs to the user. A second predetermined address bit is complemented to reverse two high order addressed word responses with two low order addressed word responses of specific address sequences. These operations are utilized in all of the required address sequences within different subgroups.

Abstract: A high performance microprocessor bus state machine couples to a synchronous local bus in common with another state machine for accessing a local memory according to a preestablished bus protocol. Circuit means cosines the state of a predetermined protocol bus signal indicating the release of the local bus and transitions of the clock signal which are not used for synchronizing the operations of the state machines. The resulting signal applies required address and control signals in advance to the local bus enabling the non-microprocessor state machine to generate the required address strobe to local memory on the next clock which follows the release of the local bus by the microprocessor which eliminates a clock cycle whenever local bus control passes from the microprocessor bus state machine to another state machine.

Abstract: A memory system tightly couples to a high performance microprocessor through a synchronous bus. The logic circuits included in the memory system generate a blipper pulse signal using successive transitions of clock pulse signals other than the edges used to synchronize microprocessor and memory operations. The blipper pulse signal is logically combined with the memory's column address strobe timing signal which is derived from the synchronizing edges of clock pulse signals which defines the duration of the column address interval required for accessing of a pair of DRAM memories during successive memory cycles for providing sequences of four memory read responses with no wait state.

Abstract: A firmware controlled microprocessor plugged into a printed circuit board received firmware signals from a control store mounted on the printed circuit board. The number of pins required for transferring firmware signals is reduced by time sharing pins with firmware signal required for the full cycle of operation and firmware signal required only during the second half of the cycle of operation.

Abstract: A central subsystem of a data processing system includes a writable control store which is loaded with firmware to control the central subsystem operations. The central subsystem logic is responsive to a sequence of commands from a system management facility to load the control store and verify that the control store firmware is loaded correctly.

Abstract: A cache memory subsystem has multilevel directory memory and buffer memory pipeline stages shared by at least a pair of independently operated central processing units and a first in first out (FIFO) device which connects to a system bus of a tightly coupled data processing system. The cache subsystem includes a number of programmable control circuits which are connected to receive signals representative of the type of operations performable by the cache subsystem. These signals are logically combined for generating an output signal indicating whether or not the contents of the directiory memory should be flushed when any one of a number of types of address or system faults has been detected in order to maintain cache coherency.

Abstract: An address path which transfers addresses from a number of sources includes an incrementing circuit. The address includes a plurality of address bits and integrity bits. The address bits are applied to the incrementing circuit while the integrity bits are applied in parallel to a programmable logic device (PLD). While the address is being transferred or incremented as required, the PLD independently generates a number of transform bits defining a characteristic of the number of address bits predicted to change state. Thereafter, the transform bits are used to transform the address integrity bits for transfer with the incremented address. The incremented address, transform bits and integrity bits are logically combined for verifying that the address was transferred and/or incremented without error.

Abstract: A data processing system includes a plurality of memory command generating units which connect to a common bus network with a number of memory subsystems. Each subsystem includes a controller which controls the operation of a number of memory module units and includes a number of queue circuits for storing memory requests to be processed. The memory controller further includes control apparatus connected to monitor bus activity. In response to certain bus activity conditions occurring during multiword transfer operations, the control apparatus operates to lengthen the time between successive multiword transfers of data to the bus so as to ensure that new requestors having lower priorities than a memory controller gain access to an available queue notwithstanding the amount of bus delay incurred in transmitting their memory requests.

Abstract: A memory system includes at least one or more memory module boards identical in construction and a single computer board containing the control circuits for controlling memory operations. Each board plugs into the main board and includes a memory section having a number of rows of memory chips and an identification section containing circuits for generating signals indicating the board density and the type of memory parts used in constructing the board's memory section. The main board control circuits include a number of decoder circuits which couple to the identification and to the memory section of each memory module board. The decoder circuits receive different address bit combinations of a predetermined multibit address portion of each memory request address.

Abstract: A remapping method and apparatus is employed by a memory controller system which includes a microprocessing section which couples to a memory section. The memory section includes a partially good bulk random access memory constructed from a plurality of bit wide chips containing a predefined small number of row or column faults randomly distributed. System columns of chips are organized into a plurality of groups or slices, each of which provide a different predetermined portion of the locations within the partially good bulk memory. A defective-free memory having substantially less capacity is similarly organized. Both memories couple to a static memory which is remapped under the control of the microprocessing section. Prior to remapping, the microprocessing section generates a "slice bit map" indicating the results of testing successive bit groups/slices within the bulk memory locations.

Abstract: A memory controller includes a partial defective bulk random access memory having a number of word locations constructed from a plurality of bit wide chips containing a predefined small number of random row or column faults. System columns of chips are organized into a plurality of groups, each group providing a different predetermined portion of the number of word locations. A defect-free memory system having substantially less capacity is similarly organized. Both memories couple to a static memory which stores column addresses associated with good memory locations and slice bit codes specifying the operational status of corresponding bit groups of word locations within both memories. During operation, read/write control circuits read and write valid words from group of bit locations from locations of both memories specified by slice bit codes.

Abstract: A memory system includes a plurality of memory controllers which connect to a common bus. Each memory controller includes reconfiguration apparatus which enables the controller when faulty to be switched off line and another controller to be substituted in its place so as to maintain system memory contiguous.