Patents by Inventor Chi Chen

Chi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12100743
    Abstract: A semiconductor device and a method for forming the same are provided. The semiconductor device includes a substrate and a gate structure. The gate structure is disposed in the substrate and includes a shielded gate, a control gate, and a plurality of insulating layers. The shielded gate includes a bottom gate and a top gate. The bottom gate includes a step structure consisting of a plurality of electrodes. A width of the electrode is smaller as the electrode is farther away from the top gate, and a width of the top gate is smaller than a width of the electrode closest to the top gate. The control gate is disposed on the shielded gate. A first insulating layer is disposed between the shielded gate and the substrate. A second insulating layer is disposed on the shielded gate. A third insulating layer is disposed between the control gate and the substrate.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: September 24, 2024
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Ying-Chi Cheng, Yu-Jen Huang, Shin-Hong Chen
  • Patent number: 12101026
    Abstract: A metal-oxide semiconductor field-effect transistor with asymmetric parallel dies and a method of using the same, including an inductor, a load recognition control unit and a metal-oxide semiconductor field-effect transistor having a first die, a second die, and a switch. The first die is larger in size than the second die. The inductor produces a voltage signal when the load changes. The switch is controlled by the load recognition control unit such that different dies are switched on under different load conditions, thereby improving efficiency under light load condition in addition to reducing volume and cost.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: September 24, 2024
    Assignee: POTENS SEMICONDUCTOR CORP.
    Inventors: Wen Nan Huang, Ching Kuo Chen, Chih Ming Yu, Hsiang Chi Meng, Tung Ming Lai
  • Patent number: 12099327
    Abstract: A holographic calling system can capture and encode holographic data at a sender-side of a holographic calling pipeline and decode and present the holographic data as a 3D representation of a sender at a receiver-side of the holographic calling pipeline. The holographic calling pipeline can include stages to capture audio, color images, and depth images; densify the depth images to have a depth value for each pixel while generating parts masks and a body model; use the masks to segment the images into parts needed for hologram generation; convert depth images into a 3D mesh; paint the 3D mesh with color data; perform torso disocclusion; perform face reconstruction; and perform audio synchronization. In various implementations, different of these stages can be performed sender-side or receiver side. The holographic calling pipeline also includes sender-side compression, transmission over a communication channel, and receiver-side decompression and hologram output.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: September 24, 2024
    Assignee: Meta Platforms Technologies, LLC
    Inventors: Albert Parra Pozo, Joseph Virskus, Ganesh Venkatesh, Kai Li, Shen-Chi Chen, Amit Kumar, Rakesh Ranjan, Brian Keith Cabral, Samuel Alan Johnson, Wei Ye, Michael Alexander Snower, Yash Patel
  • Patent number: 12099422
    Abstract: Techniques for storage testing involve: acquiring a first state of a storage system including first input/output (IO) load information; taking a first action based on the first state, the first action causing the first IO load information to be changed to second IO load information; updating the first action to be a reserved action for the first state if it is obtained based on the second IO load information that the storage system reaches a preset condition; and obtaining an action combination of a plurality of IO load information changes based on a plurality of reserved actions corresponding to a plurality of states, wherein the plurality of states include the first state. Accordingly, the most effective load combination change mode for the storage system can be found automatically and more accurately, so as to find more vulnerabilities of the storage system, thereby improving the efficiency of storage system testing.
    Type: Grant
    Filed: February 1, 2023
    Date of Patent: September 24, 2024
    Assignee: Dell Products L.P.
    Inventors: Chi Chen, Changyue Dai, En Shi, Hailan Dong
  • Patent number: 12098412
    Abstract: Disclosed herein is an isolated strain of Roseburia hominis HGM001, which is deposited at Deutsche Sammlung von Mikroorganismen and Zellkulturen GmbH under an accession number DSM 34119. A method for producing butyric acid using the isolated strain of Roseburia hominis HGM001, a fermented culture produced by the method, and a method for alleviating an inflammatory disorder using the fermented culture are also disclosed.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: September 24, 2024
    Assignee: Food Industry Research and Development Institute
    Inventors: Chien-Hsun Huang, Li-Wen Hsu, Jong-Shian Liou, I-Ching Chen, Sung-Yuan Hsieh, Chien-Chi Chen
  • Publication number: 20240307898
    Abstract: A fluid discharge device includes a hollow tubular body. The hollow tubular body defines a flow channel and has a plurality of bore holes arranged along a longitudinal direction of the hollow tubular body. The hollow tubular body includes a plurality of sections, two adjacent sections of the plurality of sections are connected by a choke ring, and the choke ring has an opening to allow a fluid to pass through. In a sectional plane perpendicular to the longitudinal direction, a sectional area of the opening is smaller than a sectional area of the flow channel.
    Type: Application
    Filed: May 1, 2023
    Publication date: September 19, 2024
    Inventors: Yu-Pao CHEN, Nian-Zu YANG, Sheng-Chi HSU
  • Publication number: 20240313263
    Abstract: A lithium-ion battery includes a positive electrode, a negative electrode, and a non-aqueous electrolyte. The positive electrode includes a positive electrode material layer, the positive electrode material layer includes a positive electrode active material, and the positive electrode active material includes LiNixCoyMnzL(1-x-y-2)O2, where L is Al, Sr, Mg. Ti, Ca, Zr, Zn, Si, Cu, V or Fe, 0.5?x?1, 0?y?0.5, 0?z?0.5, 0?x+y+z?1, and an upper limit voltage of the lithium-ion battery is ?4.2 V. The non-aqueous electrolyte includes a solvent, an electrolyte salt and a compound represented by formula 1: A-D-B-E-C, Formula 1. Based on a total mass of the non-aqueous electrolyte as 100%, the compound represented by the formula 1 is added in an amount of 0.01 to 5.0%.
    Type: Application
    Filed: December 16, 2021
    Publication date: September 19, 2024
    Inventors: Shiguang Hu, Yunxian Qian, Chaowei Cao, Pengkai Guo, Xiaoxia Xiang, Chi Wang, Shuhuai Xiang, Qun Chen, Yonghong Deng
  • Publication number: 20240311337
    Abstract: An apparatus comprises a processing device configured to detect a request for an updated snapshot schedule for an information technology asset, and to determine a current state of the information technology asset comprising a set of snapshot parameters of a current snapshot schedule and one or more performance metric values. The processing device is also configured to generate, utilizing a reinforcement learning framework, an updated parameter value for at least one of the snapshot parameters based at least in part on the current state. The processing device is further configured to monitor performance of the information technology asset utilizing the updated snapshot schedule comprising the updated parameter value for the at least one snapshot parameter, and to update the reinforcement learning framework based at least in part on a subsequent state of the information technology asset determined while monitoring performance of the information technology asset utilizing the updated snapshot schedule.
    Type: Application
    Filed: March 28, 2023
    Publication date: September 19, 2024
    Inventors: Chi Chen, En Shi, Changyue Dai
  • Publication number: 20240313706
    Abstract: The present invention provides a multi-stage amplifier, wherein the multi-stage amplifier includes a plurality of amplifier stages and a compensation circuit. The compensation circuit is coupled to an output terminal of one of the plurality of amplifier stages, and the compensation circuit includes a first auxiliary amplifier, a capacitor, a second auxiliary amplifier, a first resistor and a second resistor. The capacitor is coupled between an input terminal and an output terminal of the first auxiliary amplifier. The second auxiliary amplifier is coupled to the first auxiliary amplifier. The first resistor is coupled between an input terminal and an output terminal of the second auxiliary amplifier. The second resistor is coupled between an output terminal of the first auxiliary amplifier and a ground voltage.
    Type: Application
    Filed: February 6, 2024
    Publication date: September 19, 2024
    Applicant: MEDIATEK INC.
    Inventors: You-Shin Chen, Ya-Chi Chen, Sung-Han Wen
  • Publication number: 20240309340
    Abstract: An engineered DNA polymerase, with increased property for single molecule sequencing compared to a wild-type DNA polymerase, comprising a combination of mutation sites and functional domains, wherein the combination of mutation sites and functional domains includes thermostable mutation sites, low Kd mutation sites, exonuclease-deficient sites and DNA binding domains.
    Type: Application
    Filed: January 10, 2024
    Publication date: September 19, 2024
    Applicant: Personal Genomics Taiwan, Inc.
    Inventors: Dalton Chen, Ya-Chen Chen, Yu-Husan Lin, Yi-Ting Chou, Ting-Yueh Tsai, Chi-Fu Yen, Chao-Chi Pan
  • Publication number: 20240312893
    Abstract: An electronic device is provided. The electronic device includes a base and a semiconductor device. The base has a top surface and a bottom surface. The semiconductor device is disposed on the top surface of the base. The semiconductor device has a device edge located within the base in a top view. The base has a unit pad array which is covered by the semiconductor device and electrically connected to the semiconductor device. The unit pad array includes a first pad region composed of a first row and a second row of the unit pad array. The first pad region includes first pads for transmitting commands and addresses to and from the semiconductor device. The first row of the unit pad array is arranged so that it is closer to the device edge than the second row of the unit pad array.
    Type: Application
    Filed: March 4, 2024
    Publication date: September 19, 2024
    Inventors: Hui-Chi TANG, Shih-Yi SYU, Hao-Ju WANG, Pei-San CHEN, Duen-Yi HO
  • Publication number: 20240312427
    Abstract: An electronic device includes a panel. The panel includes a plurality of scan electrodes, a plurality of data electrodes and a cholesteric liquid crystal layer. The plurality of data electrodes and the plurality of scan electrodes are intersected with each other to define a plurality of pixels. The cholesteric liquid crystal layer is disposed between the plurality of scan electrodes and the plurality of data electrodes. In a writing mode, a first voltage difference is applied to at least one pixel disposed in a writing area, and a second voltage difference is applied to at least a portion of the other pixels disposed in a non-writing area. In an erasing mode, a third voltage difference is applied to at least one pixel disposed in an erasing area, where the first voltage difference is different from the second voltage difference, and the first voltage difference is different from the third voltage difference.
    Type: Application
    Filed: February 16, 2024
    Publication date: September 19, 2024
    Inventors: Ming-Chi GUO, Hsing-Yuan HSU, Po-Yang CHEN, I-An YAO
  • Publication number: 20240312836
    Abstract: A method includes bonding an integrated circuit die to a carrier substrate, forming a gap-filling dielectric around the integrated circuit die and along the edge of the carrier substrate, performing a bevel clean process to remove portions of the gap-filling dielectric from the edge of the carrier substrate, after performing the bevel clean process, depositing a first bonding layer on the gap-filling dielectric and the integrated circuit die, forming a first dielectric layer on an outer sidewall of the first bonding layer, an outer sidewall of the gap-filling dielectric, and the first outer sidewall of the carrier substrate; and bonding a wafer to the first dielectric layer and the first bonding layer, wherein the wafer comprises a semiconductor substrate and a second dielectric layer on an outer sidewall of the semiconductor substrate.
    Type: Application
    Filed: March 16, 2023
    Publication date: September 19, 2024
    Inventors: Ming-Tsu Chung, Yung-Chi Lin, Yi-Hsiu Chen
  • Patent number: 12094158
    Abstract: An encoded substrate to be filmed by a camera device for generating an image is provided. The encoded substrate includes a plurality of grids arranged in a form of two-dimensional array, wherein each grid includes a first pattern and a second pattern not overlapped with each other. The first pattern corresponds to a first-dimensional encoded value, and the second pattern corresponds to a second-dimensional encoded value. The image is processed by a processor for scanning the plurality of grids. In a first-dimensional direction, the processor outputs a first coordinate according to at least two first patterns corresponding to at least two consecutive grids among the plurality of grids. In a second-dimensional direction, the processor outputs a second coordinate according to at least two second patterns corresponding to at least two consecutive grids among the plurality of grids.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: September 17, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Tan-Chi Ho, Yi-Chun Chen, Wen Tsui
  • Patent number: 12093473
    Abstract: An information handling system stylus transmits a wireless signal at a writing tip to enhance touch detection of the writing tip by a touchscreen display and receives wireless signals from the touchscreen display at a receiving antenna. To enhance control of wireless energy distributed at the writing tip, the receiving antenna is selectively coupled to the writing tip, such as by transitioning from a float of the receiving antenna to an interface with the stylus power source at transmit by the writing tip. Charge at the receiving antenna helps to shape the energy distribution from the writing tip, such as to match the energy distribution of other styluses in use at the touchscreen display.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: September 17, 2024
    Assignee: Dell Products L.P.
    Inventors: Kuo-Wei Tseng, How-Lan Eric Lin, Yu-Chen Liu, Chi-Fong Lee, Wei-Chou Chen
  • Patent number: 12093552
    Abstract: An apparatus comprises a processing device configured to generate a predicted data access frequency trend pattern of a storage object for a designated period of time, the storage object being stored in a first storage tier in a clustered storage system. The processing device is also configured to classify the storage object based on the predicted data access frequency trend pattern, and to determine a given storage tier in the clustered storage system to utilize for storage of the storage object during the designated period of time based on the predicted data access frequency trend pattern. The processing device is also configured, responsive to the given storage tier being different than the first storage tier, to select a type of data movement based on the classification of the storage object and to utilize the selected type of data movement to move the storage object to the given storage tier.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: September 17, 2024
    Assignee: Dell Products L.P.
    Inventors: Chi Chen, Hailan Dong
  • Patent number: 12094887
    Abstract: A display apparatus includes a wireless transmission unit and a display panel. The display panel includes a substrate, a plurality of pixel units and a signal line. The substrate includes a display region and a periphery region. The periphery region surrounds the display region. The pixel units are disposed on the display region. Each of the pixel units includes an active device and a pixel electrode. The active device is electrically connected to the pixel electrode. The signal line is on the periphery region. As viewed from a top view, the signal line has an annular shape having a gap and surrounds the display region.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: September 17, 2024
    Assignee: E Ink Holdings Inc.
    Inventors: Chia-Chi Chang, Chih-Chun Chen, Chi-Ming Wu, Yi-Ching Wang, Jia-Hung Chen, Bo-Tsang Huang, Wei-Yueh Ku
  • Patent number: 12095254
    Abstract: An electronic device and a temperature detection device thereof are provided. The temperature detection device includes a differential stage circuit and an output stage circuit. The differential stage circuit includes a first differential end and a second differential end, and includes a cross-coupled transistor element, a first resistor and a second transistor. The cross-coupled transistor element receives a first voltage. The first resistor is coupled between the first differential end and a second voltage, and the first resistor is poly-silicon resistor. The second resistor is coupled between the second differential end and the second voltage, and the second resistor is a silicon carbide diffusion resistor. The output stage circuit generates a driving voltage according to a first control voltage on the first differential end and a second control voltage on the second differential end.
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: September 17, 2024
    Assignee: LEAP Semiconductor Corp.
    Inventors: Wei-Fan Chen, Kuo-Chi Tsai
  • Patent number: 12094948
    Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wei Chen, Wei Cheng Hsu, Hui-Chi Chen, Jian-Hao Chen, Kuo-Feng Yu, Shih-Hang Chiu, Wei-Cheng Wang, Kuan-Ting Liu, Yen-Ju Chen, Chun-Chih Cheng, Wei-Chen Hsiao
  • Patent number: D1043662
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: September 24, 2024
    Assignee: Zebra Technologies Corporation
    Inventors: Mu-Kai Shen, Lawrence Allen Stone, Man-Ching Yen, Liao-Hsun Chen, Hui-Chi Kuo, Chandra M. Nair