Abstract: A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.

Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.

Abstract: A method for manufacturing an integrated circuit is provided. The method includes depositing a floating gate electrode film over a semiconductor substrate; patterning the floating gate electrode film into at least one floating gate electrode having at least one opening therein; depositing a control gate electrode film over the semiconductor substrate to overfill the at least one opening of the floating gate electrode; and patterning the control gate electrode film into at least one control gate electrode over the floating gate electrode.

Abstract: A method for manufacturing a memory device is provided. The method includes depositing a floating gate electrode film over a semiconductor substrate; patterning the floating gate electrode film into at least one floating gate electrode having at least one opening therein; depositing a control gate electrode film over the semiconductor substrate to overfill the at least one opening of the floating gate electrode; and patterning the control gate electrode film into at least one control gate electrode over the floating gate electrode.

Abstract: A memory device includes a floating gate, a control gate, a spacer structure, a dielectric layer, and an erase gate. The floating gate is above a substrate. The floating gate has a curved sidewall. The control gate is above the floating gate. The spacer structure is in contact with the control gate and the floating gate. The spacer structure is spaced apart from the curved sidewall of the floating gate. The dielectric layer is in contact with the spacer structure and the curved sidewall of the floating gate. The erase gate is above the dielectric layer.

Abstract: Provided is a wafer container including a frame having a first sidewall and a second sidewall extending along a YZ plane; a plurality of first support structures disposed on the first sidewall and arranged along a Z direction; and a plurality of second support structures disposed on the second sidewall and arranged along the Z direction. One of the plurality of first support structures is horizontally aligned with a corresponding second support structure to constitute a wafer holder. The wafer holder includes a plurality of island structures to hold a wafer in a XY plane, and the plurality of island structures are separated to each other along a X direction. A method for holding at least one wafer is also provided.

Abstract: Provided is a wafer container including a frame and at least a pair of the stents. The frame has opposite sidewalls. The at least a pair of the stents is respectively disposed on the sidewalls of the frame, wherein the at least a pair of the stents is configured to provide at least three supporting points to support at least one wafer. A method for holding at least one wafer is also provided.

Abstract: A metal-insulator-metal (MIM) capacitor structure is provided. The MIM capacitor structure includes a first conductive layer formed over a substrate, and the first conductive layer includes a first portion and a second portion. The MIM capacitor structure also includes an insulating layer formed over the first portion of the first conductive layer and a second conductive layer formed over the first conductive layer. The second conductive layer includes a first portion and a second portion, the first portion of the second conductive layer is in direct contact with the insulating layer, and the second portion of the second conductive layer is in direct contact with the second portion of the first conductive layer.

Abstract: Provided is a wafer container including a frame and at least a pair of the stents. The frame has opposite sidewalls. The at least a pair of the stents is respectively disposed on the sidewalls of the frame, wherein the at least a pair of the stents is configured to provide at least three supporting points to support at least one wafer. A method for holding at least one wafer is also provided.

Abstract: A metal-insulator-metal (MIM) capacitor structure is provided. The MIM capacitor structure includes a first conductive layer formed over a substrate, and the first conductive layer includes a first portion and a second portion. The MIM capacitor structure also includes an insulating layer formed over the first portion of the first conductive layer and a second conductive layer formed over the first conductive layer. The second conductive layer includes a first portion and a second portion, the first portion of the second conductive layer is in direct contact with the insulating layer, and the second portion of the second conductive layer is in direct contact with the second portion of the first conductive layer.

Abstract: A method for forming a metal-insulator-metal (MIM) capacitor structure is provided. The method includes providing a substrate and forming an interconnect structure over the substrate. The interconnect structure includes a top metal layer, and wherein the top metal layer includes a first portion and a second portion. The method includes forming an insulating layer on the first portion of the top metal layer; and forming a metal pad on the insulating layer. The metal pad includes a first portion and a second portion, the MIM capacitor is constructed by the first portion of the top metal layer, the insulating layer and the first portion of the metal pad, and the second portion of the metal pad directly contacts the first portion of the metal pad and the second portion of the top metal layer.

Abstract: In a method for manufacturing a semiconductor device, a substrate is provided, and a dielectric layer is formed to cover the substrate. A recess portion is formed in the dielectric layer. A spacer is formed on a side surface of the recess portion. The dielectric layer is etched through the recess portion to form a hole in the dielectric layer to expose a portion of the substrate.

Abstract: A method for forming a metal-insulator-metal (MIM) capacitor structure is provided. The method includes providing a substrate and forming an interconnect structure over the substrate. The interconnect structure includes a top metal layer, and wherein the top metal layer includes a first portion and a second portion. The method includes forming an insulating layer on the first portion of the top metal layer; and forming a metal pad on the insulating layer. The metal pad includes a first portion and a second portion, the MIM capacitor is constructed by the first portion of the top metal layer, the insulating layer and the first portion of the metal pad, and the second portion of the metal pad directly contacts the first portion of the metal pad and the second portion of the top metal layer.

Abstract: Embodiments of mechanisms for forming a semiconductor device with metal-insulator-metal (MIM) capacitor structure are provided. The MIM capacitor structure includes a substrate; and a MIM capacitor formed on the substrate. The MIM capacitor includes a bottom electrode formed over the substrate. The bottom electrode is a top metal layer. The MIM capacitor also includes an insulating layer formed on the bottom electrode; and a top electrode formed on the insulating layer.

Abstract: In a method for manufacturing a semiconductor device, a substrate is provided, and a dielectric layer is formed to cover the substrate. A recess portion is formed in the dielectric layer. A spacer is formed on a side surface of the recess portion. The dielectric layer is etched through the recess portion to form a hole in the dielectric layer to expose a portion of the substrate.

Abstract: Embodiments of mechanisms for forming a semiconductor device with metal-insulator-metal (MIM) capacitor structure are provided. The MIM capacitor structure includes a substrate; and a MIM capacitor formed on the substrate. The MIM capacitor includes a bottom electrode formed over the substrate. The bottom electrode is a top metal layer. The MIM capacitor also includes an insulating layer formed on the bottom electrode; and a top electrode formed on the insulating layer.