Patents by Inventor Chi-Hai Kuo

Chi-Hai Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220344248
    Abstract: A package structure includes a redistribution layer, a chip assembly, a plurality of solder balls, and a molding compound. The redistribution layer includes redistribution circuits, photoimageable dielectric layers, conductive through holes, and chip pads. One of the photoimageable dielectric layers located on opposite two outermost sides has an upper surface and openings. The chip pads are located on the upper surface and are electrically connected to the redistribution circuits through the conductive through holes. The openings expose portions of the redistribution circuits to define solder ball pads. Line widths and line spacings of the redistribution circuits decrease in a direction from the solder ball pads towards the chip pads. The chip assembly is disposed on the chip pads and includes at least two chips with different sizes. The solder balls are disposed on the solder ball pads, and the molding compound at least covers the chip assembly.
    Type: Application
    Filed: April 21, 2021
    Publication date: October 27, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: John Hon-Shing Lau, Cheng-Ta Ko, Pu-Ju Lin, Kai-Ming Yang, Chi-Hai Kuo, Chia-Yu Peng, Tzyy-Jang Tseng
  • Publication number: 20220336333
    Abstract: A package structure includes at least one first redistribution layer, at least one second redistribution layer, a chip pad, a solder ball pad, a chip, a solder ball, and a molding compound. The first redistribution layer includes a first dielectric layer and a first redistribution circuit that fills a first opening and a second opening of the first dielectric layer. The first dielectric layer is aligned with the first redistribution circuit. The second redistribution layer includes a second and a third dielectric layers and a second redistribution circuit. The third dielectric layer is aligned with the second redistribution circuit. The chip pad and the solder ball pad are electrically connected to the first and the second redistribution circuits respectively. The chip and the solder ball are disposed on the chip pad and the solder ball pad respectively. The molding compound at least covers the chip and the chip pad.
    Type: Application
    Filed: April 19, 2021
    Publication date: October 20, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: John Hon-Shing Lau, Cheng-Ta Ko, Pu-Ju Lin, Kai-Ming Yang, Chia-Yu Peng, Chi-Hai Kuo, Tzyy-Jang Tseng
  • Patent number: 11476234
    Abstract: A manufacturing method of chip package structure includes following steps. A carrier is provided. A first patterned circuit layer and a first dielectric layer covering the first patterned circuit layer have been formed on the carrier. A flat structure layer is formed on the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and covers the flat structure layer and a portion of the first dielectric layer. A second patterned circuit layer is formed on the second dielectric layer. The second patterned circuit layer includes a plurality of pads. An orthographic projection of the flat structure layer on the carrier overlaps orthographic projections of the pads on the carrier. A plurality of chips are disposed on the pads. A molding compound is formed to cover the second dielectric layer and encapsulate the chips and the pads.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: October 18, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Pu-Ju Lin, Chi-Hai Kuo, Kai-Ming Yang, Cheng-Ta Ko
  • Publication number: 20220328387
    Abstract: A package carrier includes a first redistribution layer having a first upper surface and a first lower surface and including a plurality of first redistribution circuits, a plurality of conductive through holes, a plurality of photoimageable dielectric layers, and a plurality of chip pads and a second redistribution layer disposed on the first upper surface of the first redistribution layer. The second redistribution layer has a second upper surface and a second lower surface aligned with and directly connected to the first upper surface of the first redistribution layer and includes a plurality of second redistribution circuits, a plurality of conductive structures, a plurality of Ajinomoto build-up Film (ABF) layers, and a plurality of solder ball pads. A line width and a line pitch of each of the first redistribution circuits are smaller than a line width and a line pitch of each of the second redistribution circuits.
    Type: Application
    Filed: April 15, 2021
    Publication date: October 13, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: John Hon-Shing Lau, Cheng-Ta Ko, Pu-Ju Lin, Kai-Ming Yang, Chi-Hai Kuo, Chia-Yu Peng, Tzyy-Jang Tseng
  • Patent number: 11460255
    Abstract: A vapor chamber device and a manufacturing method are disclosed. The vapor chamber has a housing and multiple independent chambers. The housing includes two shells opposite to each other. The independent chambers are formed between the two shells. Each independent chamber contains a working fluid and has at least one diversion bump and a capillary structure. The diversion bump is formed on an inner surface of the second shell, and the capillary structure is mounted on the diversion bump. When the vapor chamber device is vertically mounted to a heat source, the independent chambers at an upper portion of the vapor chamber device still contain the working fluid. The working fluid in the independent chambers may not all flow to a bottom of the vapor chamber device. Therefore, a contact area between the working fluid and the heat source is increased and heat dissipation efficiency is improved.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: October 4, 2022
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Pu-Ju Lin, Ying-Chu Chen, Wei-Ci Ye, Chi-Hai Kuo, Cheng-Ta Ko
  • Publication number: 20220271208
    Abstract: A light emitting diode (LED) package structure includes a glass substrate, conductive through holes, active elements, an insulating layer, LEDs and pads. The glass substrate has an upper surface and a lower surface. The conductive through holes penetrate the glass substrate and connect the upper and the lower surfaces. The active elements are disposed on the upper surface of the glass substrate and electrically connected to the conductive through holes. The insulating layer is disposed on the upper surface and covers the active elements. The LEDs are disposed on the insulating layer and electrically connected to at least one of the active elements. The pads are disposed on the lower surface of the glass substrate and electrically connected to the conductive through holes. A source of at least one active elements is directly electrically connected to at least one of the corresponding pads through the corresponding conductive through hole.
    Type: Application
    Filed: April 12, 2021
    Publication date: August 25, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: Jeng-Ting Li, Chi-Hai Kuo, Cheng-Ta Ko, Pu-Ju Lin
  • Publication number: 20220256717
    Abstract: A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.
    Type: Application
    Filed: April 20, 2021
    Publication date: August 11, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: John Hon-Shing Lau, Cheng-Ta Ko, Pu-Ju Lin, Chi-Hai Kuo, Kai-Ming Yang, Chia-Yu Peng, Shao-Chien Lee, Tzyy-Jang Tseng
  • Publication number: 20220246810
    Abstract: A manufacturing method of a package structure is provided, which includes the following steps. A carrier having a surface is provided. A copper foil layer is laminated on the surface of the carrier. A subtractive process is performed on the copper foil layer to form a copper foil circuit layer on the carrier. The copper foil circuit layer exposes a part of the surface of the carrier. A build-up structure layer is formed on the copper foil circuit layer and the surface of the carrier. A first surface of the copper foil circuit layer is aligned with a second surface of the build-up structure layer. At least one electronic component is disposed on the build-up structure layer. A package colloid is formed to cover the electronic component and the build-up structure layer. The carrier is removed to expose the first surface of the copper foil circuit layer.
    Type: Application
    Filed: March 22, 2021
    Publication date: August 4, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Cheng-Ta Ko, Pu-Ju Lin, Chi-Hai Kuo, Kai-Ming Yang
  • Publication number: 20220146207
    Abstract: A vapor chamber device has a housing and multiple chambers. The housing includes two shells opposite to each other. The chambers are formed between the two shells. Each chamber contains a working fluid and has at least one diversion bump and a capillary structure. The diversion bump is formed on an inner surface of the second shell, and the capillary structure is mounted on the diversion bump. Since the chambers are independent from one another, when the vapor chamber device is vertically mounted to a heat source, the chambers at an upper portion of the vapor chamber device still contain the working fluid. The working fluid in the vapor chamber device may not all flow to a bottom of the vapor chamber device. Therefore, a contact area between the working fluid and the heat source is increased and heat dissipation efficiency is improved.
    Type: Application
    Filed: December 7, 2020
    Publication date: May 12, 2022
    Inventors: Pu-Ju LIN, Ying-Chu CHEN, Wei-Ci YE, Chi-Hai KUO, Cheng-Ta KO
  • Publication number: 20220071010
    Abstract: A circuit board structure includes a first sub-circuit board, a second sub-circuit board, and a third sub-circuit board. The first sub-circuit board has an upper surface and a lower surface opposite to each other, and includes at least one first conductive through hole. The second sub-circuit board is disposed on the upper surface of the first sub-circuit board and includes at least one second conductive through hole. The third sub-circuit board is disposed on the lower surface of the first sub-circuit board and includes at least one third conductive through hole. At least two of the first conductive through hole, the second conductive through hole, and the third conductive through hole are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first, second and third sub-circuit boards are electrically connected to one another.
    Type: Application
    Filed: September 26, 2021
    Publication date: March 3, 2022
    Inventors: Tzyy-Jang TSENG, Cheng-Ta KO, Pu-Ju LIN, Chi-Hai KUO, Shao-Chien LEE, Ming-Ru CHEN, Cheng-Chung LO
  • Publication number: 20210296291
    Abstract: A manufacturing method of chip package structure includes following steps. A carrier is provided. A first patterned circuit layer and a first dielectric layer covering the first patterned circuit layer have been formed on the carrier. A flat structure layer is formed on the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and covers the flat structure layer and a portion of the first dielectric layer. A second patterned circuit layer is formed on the second dielectric layer. The second patterned circuit layer includes a plurality of pads. An orthographic projection of the flat structure layer on the carrier overlaps orthographic projections of the pads on the carrier. A plurality of chips are disposed on the pads. A molding compound is formed to cover the second dielectric layer and encapsulate the chips and the pads.
    Type: Application
    Filed: April 13, 2020
    Publication date: September 23, 2021
    Applicant: Unimicron Technology Corp.
    Inventors: Pu-Ju Lin, Chi-Hai Kuo, Kai-Ming Yang, Cheng-Ta Ko
  • Publication number: 20210251107
    Abstract: A vapor chamber structure includes a thermally conductive housing, a capillary structure layer, a grid structure layer, and a working fluid. The thermally conductive housing has a sealed chamber, where a pressure in the sealed chamber is lower than a standard atmospheric pressure. The capillary structure layer is disposed in the sealed chamber. The grid structure layer is disposed in the sealed chamber and arranged along a first direction. A size of the grid structure layer is less than or equal to a size of the capillary structure layer. The working fluid fills the sealed chamber.
    Type: Application
    Filed: September 11, 2020
    Publication date: August 12, 2021
    Applicant: Unimicron Technology Corp.
    Inventors: Ra-Min Tain, Pu-Ju Lin, Cheng-Chung Lo, Chi-Hai Kuo, Cheng-Ta Ko, Tzyy-Jang Tseng, John Hon-Shing Lau
  • Publication number: 20210247147
    Abstract: A vapor chamber structure including a thermally conductive shell, a capillary structure layer, and a working fluid is provided. The thermally conductive shell includes a first thermally conductive portion and a second thermally conductive portion. The first thermally conductive portion has at least one first cavity. The second thermally conductive portion and the first cavity define at least one sealed chamber, and a pressure in the sealed chamber is lower than a standard atmospheric pressure. The capillary structure layer covers an inner wall of the sealed chamber. The working fluid is filled in the sealed chamber.
    Type: Application
    Filed: February 5, 2021
    Publication date: August 12, 2021
    Applicant: Unimicron Technology Corp.
    Inventors: Ra-Min Tain, John Hon-Shing Lau, Pu-Ju Lin, Wei-Ci Ye, Chi-Hai Kuo, Cheng-Ta Ko, Tzyy-Jang Tseng