Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.

Abstract: A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.

Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.

Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

Abstract: A package structure includes a plurality of semiconductor dies, an insulating encapsulant, a redistribution layer and a plurality of connecting elements. The insulating encapsulant is encapsulating the plurality of semiconductor dies. The redistribution layer is disposed on the insulating encapsulant in a build-up direction and electrically connected to the plurality of semiconductor dies, wherein the redistribution layer includes a plurality of conductive lines, a plurality of conductive vias and a plurality of dielectric layers alternately stacked, and a lateral dimension of the plurality of conductive vias increases along the build-up direction. The connecting elements are disposed in between the redistribution layer and the semiconductor dies, wherein the connecting elements includes a body portion joined with the semiconductor dies and a via portion joined with the redistribution layer, wherein a lateral dimension of the via portion decreases along the build-up direction.

Abstract: An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.

Abstract: An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.

Abstract: A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.

Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: The semiconductor structure includes a plurality of first dies, a plurality of second dies disposed over each of the first dies, and a dielectric material surrounding the plurality of first dies and the plurality of second die. Each of the second dies overlaps a portion of each first die.

Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: A semiconductor package includes a die, an insulation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The insulation layer is disposed on the die and includes a plurality of openings exposing the first pads and the second pads. The first electrical conductive vias and the second electrical conductive vias are disposed in the openings and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the insulation layer. The connecting pattern is disposed on the insulation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.

Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a die stack disposed over the substrate, a heat spreader disposed over the substrate and having a surface facing the substrate, and a thermal interface material (TIM) disposed between the die stack and the heat spreader. A bottommost die of the die stack includes a surface exposed from remaining dies of the die stack from a top view perspective; and the TIM is in contact with the exposed surface of the bottommost die and the surface of the heat spreader, and is in contact with a sidewall of at least one of the plurality of dies of the die stack.

Abstract: An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.

Abstract: A semiconductor structure includes a plurality of first dies, a second die disposed over each of the first dies, and a dielectric material surrounding the first dies and the second die. The second dies overlaps a portion of each of the first dies. A dimension of the second die is different from a dimension of the first dies.

Abstract: A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.