Abstract: A method for CMP includes following operations. A metal stack is received. The metal layer stack includes at least a first metal layer and a second metal layer, and a top surface of the first metal layer and a top surface of the second metal layer are exposed. A protecting layer is formed over the second metal layer. A portion of the first metal layer is etched. The protecting layer protects the second metal layer during the etching of the portion of the first metal layer. A top surface of the etched first metal layer is lower than a top surface of the protecting layer. The protecting layer is removed from the second metal layer.

Abstract: A method for manufacturing a golf ball having a non-uniform dot pattern is provided. Firstly, a semi-finished product of a golf ball is provided, which includes a ball body and a base layer covering an outer surface of the ball body. After that, the semi-finished product of the golf ball is rotated at a predetermined rotation speed, and a color paint is applied to the semi-finished product of the golf ball in a spraying manner from each of an upper position and a lower position.

Abstract: A method of manufacturing a semiconductor device includes forming a transistor layer with an M*1st layer that overlays the transistor layer with one or more first conductors that extend in a first direction. Forming an M*2nd layer that overlays the M*1st layer with one or more second conductors which extend in a second direction. Forming a first pin in the M*2nd layer representing an output pin of a cell region. Forming a long axis of the first pin substantially along a selected one of the one or more second conductors. Forming a majority of the total number of pins in the M*1st layer, the forming including: forming second, third, fourth and fifth pins in the M*1st layer representing corresponding input pins of the circuit; and forming long axes of the second to fifth pins substantially along corresponding ones of the one or more first conductors.

Abstract: Methods and apparatus are provided for providing UE EPS capability information and receiving non-access stratum (NAS) security algorithm information for an interworking procedure in the 5GS network. In one novel aspect, the UE provides the UE EPS capability information in cleartext before the security mode procedure, and the NAS security algorithm information is included in a security mode command message during the security mode procedure. In one embodiment, the UE EPS capability information is an S1 mode indicator or the 5GMM capability information including the Si mode indicator. In another novel aspect, the network provides the NAS security algorithm information before interworking procedure from 5GS to LTE. In one embodiment, the network provides the NAS security algorithm information in the Registration Accept message. In another embodiment, the network provides the NAS security algorithm information in handover procedure from the 5GS to LTE.

Abstract: The present disclosure provides a method of forming an interconnect structure. The method includes forming a metal layer over a substrate, the metal layer including a first metal; forming a capping layer on the metal layer; patterning the capping layer and the metal layer, thereby forming trenches in the metal layer; depositing a first dielectric layer in the trenches; removing the capping layer, resulting in the first dielectric layer protruding from a top surface of the metal layer; depositing a second dielectric layer over the first dielectric layer and the metal layer; forming an opening in the second dielectric layer, thereby partially exposing the top surface of the metal layer; and forming a conductive feature in the opening and in electrical coupling with the metal layer, the conductive feature including a second metal.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.

Abstract: A method of fabricating a semiconductor device includes forming a first film having a first film stress type and a first film stress intensity over a substrate and forming a second film having a second film stress type and a second film stress intensity over the first film. The second film stress type is different than the first film stress type. The second film stress intensity is about same as the first film stress intensity. The second film compensates stress induced effect of non-flatness of the substrate by the first film.

Abstract: An integrated circuit includes a first type-one transistor, a second type-one transistor, a first type-two transistor, a second type-two transistor, a third type-one transistor, a fourth type-one transistor, and a fifth type-one transistor. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The first active-region of the third type-one transistor is connected with an active-region of the first type-one transistor. The second active-region and the gate of the third type-one transistor are connected together. The first active-region of the fifth type-one transistor is connected with the gate of the third type-one transistor. The second active-region of the fifth type-one transistor is configured to have a first supply voltage of a second power supply.

Abstract: A method for manufacturing a thick polyimide film includes providing a first and second laminated structures. The first and second laminated structures are heated, and the heated first and second laminated structures are wound together to form a third laminated structure. The first polyamic acid gel film of the heated first laminated structure and the second polyamic acid gel film of the heated second laminated structure are overlapped and bonded together to form a third polyamic acid gel film. Two third laminated structures are wound together to form a fourth polyamic acid gel film. A dehydration ring-closure imidization reaction is applied to the fourth polyamic acid gel film by heating to obtain the thick polyimide film. A thick polyimide film manufactured by the method is also disclosed.

Abstract: The present invention relates to a coating process and a process system for a cable, and a cable manufactured thereby. The process includes: (1) providing the cable; (2) transporting the cable into immersion device, the cable immerged in first solution to form first coating layer thereon; (3) transporting the cable out of the immersion; (4) transporting the cable into coating device through third wire die, the cable immerged in second solution to form second coating layer thereon, the second layer is attached to the cable through the first layer; (5) transporting the cable out of the coating device through fourth wire die, fourth aperture diameter of the fourth wire die is larger than third aperture diameter of the third wire die; and (6) heating the cable to cure the second coating layer. The system includes: a cable providing device; an immersion device; a coating device; and a heating device.

Abstract: A light-emitting device includes a first carrier, which includes a side surface between a first surface and a second surface, upper conductive pads on the first surface, and lower conductive pads under the second surface; a RDL pixel package includes a RDL which includes bonding pads and bottom electrodes, and the light-emitting units on the RDL, and connected to the bonding pads. A light-transmitting layer on the RDL and covers the light-emitting units, an upper surface, a lower surface, and a lateral surface between the upper surface and the lower surface. The RDL pixel package is on the first surface and electrically connected to the upper conductive pads. A protective layer covers the first surface and contacting the side surface of the RDL pixel package. The lower electrodes and the upper conductive pads are connected, and the distance between two adjacent bonding pads is less than 30 ?m.

Abstract: A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Abstract: A method for CMP includes following operations. A dielectric structure is received. The dielectric structure includes a metal layer stack formed therein. The metal layer stack includes at least a first metal layer and a second metal layer, and the first metal layer and the second metal layer are exposed through a surface of the dielectric structure. A first composition is provided to remove a portion of the first metal layer from the surface of the dielectric structure. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed from the second metal layer. A CMP operation is performed to remove a portion of the second metal layer. In some embodiments, the protecting layer protects the second metal layer during the removal of the portion of the first metal layer.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first conductive pattern on a substrate, a second conductive pattern above the first conductive pattern, and a third conductive pattern above the first conductive pattern, all extending along a first direction. The first conductive pattern is electrically connected in parallel to the second conductive pattern and the third conductive pattern.

Abstract: A method of forming a deep trench isolation in a radiation sensing substrate includes: forming a trench in the radiation sensing substrate; forming a corrosion resistive layer in the trench, in which the corrosion resistive layer includes titanium carbon nitride having a chemical formula of TiCxN(2-x), and x is in a range of 0.1 to 0.9; and filling a reflective material in the trench and over the corrosion resistive layer.

Abstract: An iterative detection and decoding (IDD) circuit is provided. The iterative detection and decoding (IDD) circuit is configured to perform M outer iterations on a received signal, and Ni inner iterations are performed during the ith outer iteration of the M outer iterations, where M is an integer greater than 1, i is an integer less than or equal to M, and N1 to NM are integers and include at least two different values.

Abstract: A method for manufacturing a golf ball having a multi-layered pattern is provided. Firstly, a semi-finished product of the golf ball is provided and includes a ball-shaped body and a base layer covering an outer surface of the ball-shaped body. Then, the semi-finished product of the golf ball is rotated at a predetermined rotation speed, and a color paint is applied to the semi-finished product of the golf ball by spraying from each of an upper position, a middle position, and a lower position. The multi-layered pattern includes an upper-layer pattern area, a mid-layer pattern area, and a lower-layer pattern area that are different in color from each other.

Abstract: Methods and apparatus are provided for providing UE EPS capability information and receiving non-access stratum (NAS) security algorithm information for an interworking procedure in the 5GS network. In one novel aspect, the UE provides the UE EPS capability information in cleartext before the security mode procedure, and the NAS security algorithm information is included in a security mode command message during the security mode procedure. In one embodiment, the UE EPS capability information is an S1 mode indicator or the 5GMM capability information including the Si mode indicator. In another novel aspect, the network provides the NAS security algorithm information before interworking procedure from 5GS to LTE. In one embodiment, the network provides the NAS security algorithm information in the Registration Accept message. In another embodiment, the network provides the NAS security algorithm information in handover procedure from the 5GS to LTE.

Abstract: Some embodiments of the present disclosure provide a back side illuminated (BSI) image sensor. The back side illuminated (BSI) image sensor includes a semiconductive substrate and an interlayer dielectric (ILD) layer at a front side of the semiconductive substrate. The ILD layer includes a dielectric layer over the semiconductive substrate and a contact partially buried inside the semiconductive substrate. The contact includes a silicide layer including a predetermined thickness proximately in a range from about 600 angstroms to about 1200 angstroms.

Abstract: A method of forming a deep trench isolation in a radiation sensing substrate includes: forming a trench in the radiation sensing substrate; forming a corrosion resistive layer in the trench, in which the corrosion resistive layer includes titanium carbon nitride having a chemical formula of TiCxN(2-x), and x is in a range of 0.1 to 0.9; and filling a reflective material in the trench and over the corrosion resistive layer.