Abstract: The present invention provides an electrostatic charge detecting packaging device comprising a carrier, multiple dies, and multiple electrostatic-charge-sensitive components; the carrier has a surface; the dies are mounted on the surface of the carrier; and the electrostatic-charge-sensitive components are mounted on the surface of the carrier; since an electrostatic voltage tolerance of each of the electrostatic-charge-sensitive components is lower than an electrostatic voltage tolerance of each of the dies, accumulated electrostatic charges are more likely to discharge towards the electrostatic-charge-sensitive components than towards the dies, and as such, by electrically testing whether the electrostatic-charge-sensitive components are functioning normally when packaging the dies, the present invention allows personnel to debug for knowing which packaging steps exactly cause more serious problems that lead to damaging electrostatic discharges in the dies.

Abstract: A recognition method, for recognizing biological characteristic, includes the following: providing a database, wherein the database comprises a plurality of set biological characteristics and a plurality of function relationship between one of the set biological characteristics and a function; capturing, by an electronic device, a to-be-recognized biological characteristic of a user; comparing, by the first electronic device, the to-be-recognized biological characteristic with the set biological characteristics in the database; determining, by the electronic device, whether the to-be-recognized biological characteristic matches a matched one of the set biological characteristics; and when the to-be-recognized biological characteristic matches the matched one of the set biological characteristics, performing, by the electronic device or another electronic device, the function.

Abstract: An electronic device includes a first electronic element and a second electronic element. The first electronic element stores a pairing information. The second electronic element is detachably disposed on the first electronic element. When the second electronic element is electrically connected with the first electronic element, the first electronic element is wirelessly communicated with a third electronic element. When the second electronic element is detached from the first electronic element, the second electronic element is wirelessly communicated with the third electronic element through the pairing information.

Abstract: A recognition method, for recognizing biological characteristic, includes the following: providing a database, wherein the database comprises a plurality of set biological characteristics and a plurality of function relationship between one of the set biological characteristics and a function; capturing, by an electronic device, a to-be-recognized biological characteristic of a user; comparing, by the first electronic device, the to-be-recognized biological characteristic with the set biological characteristics in the database; determining, by the electronic device, whether the to-be-recognized biological characteristic matches a matched one of the set biological characteristics; and when the to-be-recognized biological characteristic matches the matched one of the set biological characteristics, performing, by the electronic device or another electronic device, the function.

Abstract: The invention provides method and associated signal system improving mitigation of injection-pulling effect for an oscillator which generates an output clock under control of a control signal. The method may include: by a loop filter, filtering a deviation signal to form a filtered signal; by a SIL (self-injection locked) controller, forming an auxiliary signal which tracks the deviation signal or a phase difference between a reference clock and an output signal resulting from the output clock; and, forming the control signal by summing the filtered signal and the auxiliary signal.

Abstract: The invention provides method and associated signal system improving mitigation of injection-pulling effect for an oscillator which generates an output clock under control of a control signal. The method may include: by a loop filter, filtering a deviation signal to form a filtered signal; by a SIL (self-injection locked) controller, forming an auxiliary signal which tracks the deviation signal or a phase difference between a reference clock and an output signal resulting from the output clock; and, forming the control signal by summing the filtered signal and the auxiliary signal.

Abstract: A frequency-generating circuit includes a frequency synthesizer circuit and a controller. The frequency synthesizer circuit generates a radio-frequency clock signal according to a reference clock signal and a channel number. The controller is coupled to the frequency synthesizer circuit, generates a power-down control signal for controlling at least a portion of the frequency synthesizer circuit to power down. The frequency synthesizer circuit includes an accumulator for generating an accumulated value according to the channel number. The frequency synthesizer circuit generates the radio-frequency clock signal according to the reference clock signal and the accumulated value. The controller maintains the accumulated value of the accumulator when the portion of the frequency synthesizer circuit powers down.

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Abstract: A transmit power measurement apparatus includes a transmit power detection path, a compensation circuit and a tracking circuit. The compensation circuit includes a programmable filter device and a compensation controller. The programmable filter device generates a filter output. The compensation controller sets the programmable filter device at least based on a frequency response of the transmit power detection path. The tracking circuit generates a transmit power tracking result at least based on the filter output.

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Abstract: A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

Abstract: A method of estimating gain of a time-to-digital converter (TDC) includes: capturing a TDC output sample; calculating a gradient in response to the TDC output sample; and adjusting a TDC normalizing gain based on the calculating step. Another method of calibrating gain of a TDC includes: capturing a phase error which is derived from a TDC output sample, a reference phase and a variable phase; calculating a gradient in response to the phase error; and adjusting a TDC normalizing gain based on the calculating step.

Abstract: A digital transmitter includes: a plurality of adjustable delay lines arranged to delay a plurality of digital input signals by a plurality of delay times to generate a plurality of delayed digital input signals respectively; a plurality of converting devices arranged to convert the plurality of delayed digital input signals into a plurality of converting signals respectively; and a calibration device arranged to adjust a delay time of at least one adjustable delay line in the plurality of adjustable delay lines to make the plurality of converting devices convert the plurality of delayed digital input signals at respective desire time points.

Abstract: A digital transmitter includes: a plurality of converting devices arranged to generate a plurality of converting signals according to a plurality of digital input signals; a compensation device arranged to generate at least one compensation signal according to the plurality of digital input signals; and a combining circuit arranged to output an amplified output signal according to the plurality of converting signals and the at least one compensation signal.

Abstract: A transmitter system includes a digital phase rotator, a phase rotation controller, and a digital radio-frequency (RF) transmitter. The digital phase rotator receives a first constellation data, and applies a digital phase rotation to the received first constellation data to generate a second constellation data. The phase rotation controller configures the digital phase rotation. The digital RF transmitter receives a digital input data derived from the second constellation data, and converts the digital input data into an analog RF output.

Abstract: A frequency modulator includes a digitally-controlled oscillator (DCO) arranged for producing a frequency deviation in response to a modulation tuning word and a phase-locked loop (PLL) tuning word. In addition, another frequency modulator includes a DCO and a DCO interface circuit. The DCO is arranged for producing a frequency deviation in response to an integer tuning word and a fractional tuning word. The DCO interface circuit is arranged for generating the integer tuning word and the fractional tuning word to the DCO, wherein the fractional tuning word is obtained through asynchronous sampling of a fixed-point tuning word.

Abstract: A frequency modulator includes a digitally-controlled oscillator (DCO) arranged for producing a frequency deviation in response to a modulation tuning word and a phase-locked loop (PLL) tuning word. In addition, another frequency modulator includes a DCO and a DCO interface circuit. The DCO is arranged for producing a frequency deviation in response to an integer tuning word and a fractional tuning word. The DCO interface circuit is arranged for generating the integer tuning word and the fractional tuning word to the DCO, wherein the fractional tuning word is obtained through asynchronous sampling of a fixed-point tuning word.

Abstract: A frequency modulating path for generating a frequency modulated clock includes a direct feed input arranged for directly modulating frequency of an oscillator, and a compensating feed input arranged for compensating effects of frequency modulating on a phase error; wherein the compensating feed input is resampled by a down-divided clock that is an integer edge division of the oscillator. A reference phase generator for generating a reference phase output includes a resampling circuit, an accumulator and a sampler. The resampling circuit is for resampling a modulating frequency command word (FCW) input to produce a plurality of samples. The accumulator is for accumulating the samples to generate an accumulated result. The sampler is for sampling the accumulated result according to a frequency reference clock, and accordingly generating a sampled result, wherein the reference phase output is updated according to at least the sampled result.