Abstract: The disclosure is directed to a memory storage apparatus having a dynamic data repair mechanism. The memory storage apparatus includes a connection interface; a memory array; and a memory control circuit configured at least to: receive, from the connection interface, a write command which includes a user data and an address of the user data; encode the user data as a codeword which includes the user data and parity bits; write the codeword, in a first memory location of the memory array, as a written codeword; perform a read procedure of the written codeword to determine whether the written codeword is erroneously written; and store a redundant codeword of the user data in a second memory location in response to having determined that the written codeword is erroneously written.

Abstract: A memory device and a multiple cells error correction in a memory cell is provided. The memory device includes a plurality of memory cells and a memory control circuit. Each of the memory cells includes a first type physical cell and a second type physical cell. The memory control circuit is coupled to each of the memory cells. The memory control circuit writes a writing data into the first type physical cell and verifies the data stored in the first type physical cell is same as the writing data or not. The writing data is set and processed by performing a write operation. The memory control circuit writes the writing data into the second type physical cell when the data stored in the first type physical cell is not same as the writing data.

Abstract: An encoding method for a memory storage apparatus adopting an ECC algorithm is provided. The memory storage apparatus comprises an ECC encoder. The encoding method includes: receiving a write command comprising a write address and a write data; reading an existing codeword; attaching a flip bit to the write data; encoding the write data and the flip bit to generate parity bits based on the ECC algorithm by the ECC encoder and attaching the write data and the flip bit to the plurality of parity bits to generate a new codeword; flipping the new codeword based on a number of bits among selected bits required to be changed from the existing codeword to the new codeword; and writing one of the new codeword and the flipped new codeword to the write address. In addition, a memory storage apparatus using the encoding method is provided.

Abstract: The codeword accessing method including: receiving a write data with M message bits; generating parity information with N-M bits based on an error correction algorithm and the M message bits, where N and M are positive integers; transforming the M message bits and the parity information to a scrambled codeword with N bits by a scrambling operation, where the scrambled codeword contains only a part of the M message bits; and writing the scrambled codeword into a memory device.

Abstract: A resistive memory with a self-termination control function and a self-termination control method for a resistive memory are provided. At least one memory cell comprises a cell transistor and a resistive element. A termination switch coupled to a source line terminates a write operation according to a comparison result. The comparator compares a voltage of a source line node with a reference voltage to output the comparison result, wherein the source line node is between the at least one memory cell and the termination switch, and the voltage of the source line node responses to the resistance of the resistive element. The variable resistance circuit provides an effective resistance according to a target resistance of the resistive element and outputs a reference current. The reference voltage node is coupled to the variable resistance circuit and the comparator and receives the reference current to provide the reference voltage to the comparator.

Abstract: The invention provides a data accessing method for a memory apparatus. The data accessing method includes: performing a reading operation on the memory apparatus based on an address information to obtain a codeword and an indicator, where the indicator corresponds to the codeword; enabling a first error correction code (ECC) operation or second ECC operation to be operated on the codeword for generating an error corrected data, wherein, the first ECC operation corrects less bits than the second ECC operation.

Abstract: The invention provides a memory apparatus including a memory cell array and a hierarchical error correction code (ECC) layer. The hierarchical ECC layer, includes N layers of ECC coder-decoder, wherein the hierarchical ECC layer enables one of the N layers to operate an encoding or decoding operation on processed data, and the hierarchical ECC layer enables another one of the N layers merely when the error bit number of the processed data reaches to N?1 pre-set error correction number(s), and N is a positive integer larger than 1.

Abstract: The disclosure is directed to a RRAM having a plurality of 1TnR structures. In an aspect, the disclosure provides a RRAM including a plurality of 1TnR structures which includes a first 1TnR structure which includes a first transistor having a first gate terminal connected to a first word line, a first drain terminal, and a first source terminal connected to a source line, wherein the source line is connected to each of the plurality of 1TnR structures; and a first N parallel resistors group including a first resistor and a second resistor which are connected to the first drain terminal and connected to each other in parallel, wherein the first resistor is connected to a first bit line, the second resistor is connected to a second bit line, and N is an integer greater than one.

Abstract: A memory device and a method of assisting a read operation in the memory device are introduced. The memory device may include a logic circuit, a charge pump, a switch and a sense amplifier. The logic circuit is configured to receive at least one input signal and perform a logic operation on the at least one input signal to output an enable signal. The charge pump is coupled to the logic circuit and is configured to generate a boost voltage according to the enable signal. The switch is coupled between the charge pump and a sensing power supply line, and is configured to control an electrical connection between the charge pump and the sensing power supply line according to the enable signal to supply the boost voltage to the sensing power supply line. The sense amplifier is configured to perform a read operation using the boost voltage from the sensing power supply line.

Abstract: The disclosure provides a memory device including: a connection interface; a memory array associated with a parameter; and a memory control circuit configured at least to: receive operations, each of the operations being a read operation or a write operation, through the connection interface to perform the operations on the memory array; detect, based on performing the operations on the memory array, a read error which is either a binary 0 read error or a binary 1 read error; update the error counter by incrementing an counter value of the error counter in response to the read error being the binary 1 read error and decreasing the counter value in response to the read error being the binary 0 read error; and adjust the parameter in response to the counter value having reached a positive predetermined threshold or a negative predetermined threshold.

Abstract: The invention provides a memory apparatus including a memory cell array and a hierarchical error correction code (ECC) layer. The hierarchical ECC layer, includes N layers of ECC coder-decoder, wherein the hierarchical ECC layer enables one of the N layers to operate an encoding or decoding operation on processed data, and the hierarchical ECC layer enables another one of the N layers merely when the error bit number of the processed data reaches to N?1 pre-set error correction number(s), and N is a positive integer larger than 1.

Abstract: The codeword accessing method including: receiving a write data with M message bits; generating parity information with N-M bits based on an error correction algorithm and the M message bits, where N and M are positive integers; transforming the M message bits and the parity information to a scrambled codeword with N bits by a scrambling operation, where the scrambled codeword contains only a part of the M message bits; and writing the scrambled codeword into a memory device.

Abstract: The invention provides a resistive memory with better area efficiency without degrading reliability, which includes an array area, word lines, a local bit line, source lines, and a shared bit line. In the array area, memory cells are arranged in a matrix, and each memory cells includes a variable resistance element and an accessing transistor. The word lines extend in a row direction of the array area and are connected to the memory cells in the row direction. The local bit line extends in a column direction of the array area. The source lines extend in the column direction and are connected to first electrodes of the memory cells in the column direction. The shared bit line is connected to the local bit line. The shared bit line extends in the row direction and is connected to second electrodes of the memory cells in the row direction.

Abstract: An option code providing circuit includes a plurality of resistive random access memory cells and a controller. The controller determines whether to provide a control signal to operate a heavy forming operation on the resistive random access memory cells or not. Wherein, the controller performs a read operation on the resistive random access memory cells to determine a bit number of the resistive random memory cell which is heavy formed, and the option code is determined by the bit number of resistive random access memory cell which is heavy formed or a bit number of the resistive random access memory cell which is not heavy formed.

Abstract: A PUF code providing apparatus includes a non-volatile memory cell pair and a data sensing circuit. The sensing circuit is coupled to the non-volatile memory cell pair, reads two initial statuses of the non-volatile memory cell pair and generates a PUF code by comparing the two initial statuses of the non-volatile memory cell pair.

Abstract: The disclosure is directed to a memory storage apparatus having a dynamic data repair mechanism. The memory storage apparatus includes a connection interface; a memory array; and a memory control circuit configured at least to: receive, from the connection interface, a write command which includes a user data and an address of the user data; encode the user data as a codeword which includes the user data and parity bits; write the codeword, in a first memory location of the memory array, as a written codeword; perform a read procedure of the written codeword to determine whether the written codeword is erroneously written; and store a redundant codeword of the user data in a second memory location in response to having determined that the written codeword is erroneously written.

Abstract: An encoding method for a memory storage apparatus adopting a Lien ECC scheme is provided. The memory storage apparatus comprises an ECC encoder using a Lien Code. The encoding method includes: receiving a write command comprising a write address and a write data; reading an existing codeword comprising a first flip bit indicating bit-flipping of the existing codeword and flipping bits of the existing codeword based on the first flip bit; encoding the write data into a new codeword based on a Lien Code by an ECC encoder, and flipping bits of the new codeword based on a number of bits required to be changed from the existing codeword to the new codeword; and writing the new codeword comprising a first flip bit indicating bit-flipping of the new codeword to the write address In addition, a memory storage apparatus using the encoding method based on the Lien Code is provided.

Abstract: An operating method of a resistive memory element includes: performing a thermal step on the resistive memory element; performing a set and reset cycle operation on the resistive memory element to increase a read margin of the resistive memory element after a thermal step; and determining whether the resistive memory element passes a read margin verification.

Abstract: An encoding method for a memory storage apparatus adopting an ECC algorithm is provided. The memory storage apparatus comprises an ECC encoder. The encoding method includes: receiving a write command comprising a write address and a write data; reading an existing codeword; attaching a flip bit to the write data; encoding the write data and the flip bit to generate parity bits based on the ECC algorithm by the ECC encoder and attaching the write data and the flip bit to the plurality of parity bits to generate a new codeword; flipping the new codeword based on a number of bits among selected bits required to be changed from the existing codeword to the new codeword; and writing one of the new codeword and the flipped new codeword to the write address. In addition, a memory storage apparatus using the encoding method is provided.

Abstract: A physical unclonable function code generating method includes: providing a plurality of non-volatile memory cell pairs including a first non-volatile memory cell and a second non-volatile memory cell; comparing an initial state of the first non-volatile memory cell with an initial state of the second non-volatile memory cell, and generating a first physical unclonable function code according to a comparison result of the state; calculating a formation ratio difference of a logical level in the first physical unclonable function code; and adjusting the formation ratio difference by interactively performing forming operations on the first non-volatile memory cell and the second non-volatile memory cell when the formation ratio difference is greater than or equal to a ratio threshold.