Patents by Inventor Chi-Ting Cheng

Chi-Ting Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230023218
    Abstract: The embodiments of the present disclosure provide a cell culture composition and a use thereof, and the cell culture composition includes a culture medium and mitochondria. The cell culture composition including mitochondria can promote cell growth and improve the function of the damaged or aged stem cells, thereby improving overall cell growth.
    Type: Application
    Filed: September 19, 2022
    Publication date: January 26, 2023
    Applicant: TAIWAN MITOCHONDRION APPLIED TECHNOLOGY CO., LTD.
    Inventors: Han-Chung CHENG, Chih-Kai HSU, Hui-Ching TSENG, Shun-Chieh YANG, Chi-Tang TU, Szu-Ting LIU, Li-Hsin YAO
  • Publication number: 20230003625
    Abstract: An agent for cryopreservation includes trehalose, HEPES and serum albumin. The agent for cryopreservation does not include potassium chloride, sodium chloride, ethylene glycol, ethylene glycol tetraacetic acid and ethylenediaminetetraacetic acid.
    Type: Application
    Filed: August 26, 2022
    Publication date: January 5, 2023
    Applicant: TAIWAN MITOCHONDRION APPLIED TECHNOLOGY CO., LTD.
    Inventors: Chi-Tang TU, Szu-Ting LIU, Li-Hsin YAO, Han-Chung CHENG
  • Patent number: 11545560
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: January 3, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Chih Chuang, Chia-Jong Liu, Kuang-Hsiu Chen, Chung-Ting Huang, Chi-Hsuan Tang, Kai-Hsiang Wang, Bing-Yang Jiang, Yu-Lin Cheng, Chun-Jen Chen, Yu-Shu Lin, Jhong-Yi Huang, Chao-Nan Chen, Guan-Ying Wu
  • Patent number: 11483493
    Abstract: A method of image conversion includes selecting a set of pixels from a source image, storing the set of pixels in a memory, determining whether the set of pixels includes at least one pixel requiring coordinate conversion by querying a predetermined mapping table, if the set of pixels includes the at least one pixel requiring coordinate conversion, converting the coordinates of the at least one pixel, and after converting the coordinates of the at least one pixel, removing the set of pixels from the memory.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: October 25, 2022
    Assignee: WELTREND SEMICONDUCTOR INC.
    Inventors: Hsuan-Ying Chen, Chun-Ting Lin, Hsiu-Yuan Fan, Chi-Cheng Cheng, Hung-Chih Chiang
  • Patent number: 11441221
    Abstract: In an embodiment, a method of manufacturing a semiconductor device includes preparing a deposition processing chamber by flowing first precursors to form a dielectric coat along an inner sidewall of the deposition processing chamber and flowing a second precursor to form a hydrophobic layer over the dielectric coat. In addition one or more deposition cycles are performed. Next, the second precursor is flowed again to repair the hydrophobic layer.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Hsien Cheng, Chung-Ting Ko, Tsung-Hsun Yu, Tze-Liang Lee, Chi On Chui
  • Patent number: 11436483
    Abstract: An accelerator for neural network computing includes hardware engines and a buffer memory. The hardware engines include a convolution engine and at least a second engine. Each hardware engine includes circuitry to perform neural network operations. The buffer memory stores a first input tile and a second input tile of an input feature map. The second input tile overlaps with the first input tile in the buffer memory. The convolution engine is operative to retrieve the first input tile from the buffer memory, perform convolution operations on the first input tile to generate an intermediate tile of an intermediate feature map, and pass the intermediate tile to the second engine via the buffer memory.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: September 6, 2022
    Assignee: MEDIATEK INC.
    Inventors: Yu-Ting Kuo, Chien-Hung Lin, Shao-Yu Wang, ShengJe Hung, Meng-Hsuan Cheng, Chi-Ta Wu, Henrry Andrian, Yi-Siou Chen, Tai-Lung Chen
  • Publication number: 20220232694
    Abstract: Provided is a circuit board, including a first substrate, a second substrate, a third substrate, a fourth substrate, multiple conductive structures, and a conductive via structure. The second substrate is disposed between the first substrate and the third substrate. The third substrate is disposed between the second substrate and the fourth substrate. The third substrate has an opening penetrating the third substrate and includes a first dielectric layer filling the opening. The conductive via structure penetrates the first substrate, the second substrate, the first dielectric layer of the third substrate, and the fourth substrate, and is electrically connected to the first substrate and the fourth substrate to define a signal path. The first substrate, the second substrate, the third substrate and the fourth substrate are electrically connected through the conductive structures to define a ground path, and the ground path surrounds the signal path.
    Type: Application
    Filed: October 8, 2021
    Publication date: July 21, 2022
    Applicant: Unimicron Technology Corp.
    Inventors: Chih-Chiang Lu, Heng-Ming Nien, Ching-Sheng Chen, Ching Chang, Ming-Ting Chang, Chi-Min Chang, Shao-Chien Lee, Jun-Rui Huang, Shih-Lian Cheng
  • Patent number: 11379245
    Abstract: A controlling device and a drone controlling method are provided. The method includes: detecting a first program block that is towed in a human machine interface; bonding the first program block to a bonding position corresponding to at least one target program block in the human machine interface to obtain a first program block sequence composed of a plurality of second program blocks; and transmitting a plurality of control commands respectively corresponding to the plurality of second program blocks or controlling a virtual drone to execute the plurality of control commands according to a sequence order of the plurality of second program blocks in the first program block sequence.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: July 5, 2022
    Assignee: Wistron Corporation
    Inventors: Kuan-Hung Chen, Chia-Yin Li, Chi-Tung Wang, Hong-Ting Cheng, Chih-Ming Chang, Yen-Hung Chen
  • Patent number: 11087833
    Abstract: A power management circuit suitable for a memory device and a memory device is provided. The power management circuit includes a first logic circuit, a second logic circuit, and a transmission gate. The first logic circuit is configured to receive an inverted first input signal and a second input signal and generates a first output signal. The second logic circuit is configured to receive a first input signal and the second input signal and generates a second output signal. The transmission gate is configured to receive the first output signal and generates a control signal to at least one power transistor coupled between the power management circuit and the memory device. During a standby mode, the power transistor is turned on to make a first voltage equal to a predetermined voltage and during a sleep mode, the control signal is coupled to a first voltage. The predetermined voltage is greater than the first voltage.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chen Kuo, Cheng-Hung Lee, Chi-Ting Cheng, Hua-Hsin Yu, Wei-Jer Hsieh, Yu-Hao Hsu, Yang-Syu Lin, Che-Ju Yeh
  • Publication number: 20210217446
    Abstract: A device disclosed includes first and second rows of memory cells, a first data line, and a first continuous data line. The first and second rows of memory cells are arranged in a first sub-bank and a second sub-bank, separated from the first sub-bank, respectively. The first data line is arranged across the first sub-bank and coupled to a first memory cell in the first row of memory cells. The first continuous data line includes a first portion arranged across the first sub-bank and a second portion arranged across the second sub-bank. The first continuous data line is coupled to a second memory cell in the second row of memory cells. The first portion of the first continuous data line is disposed in a first metal layer. The first data line and the second portion of the first continuous data line are in a second metal layer.
    Type: Application
    Filed: March 26, 2021
    Publication date: July 15, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung CHANG, Cheng-Hung LEE, Chi-Ting CHENG, Hung-Jen LIAO, Jhon-Jhy LIAW, Yen-Huei CHEN
  • Publication number: 20210125662
    Abstract: A power management circuit suitable for a memory device and a memory device is provided. The power management circuit includes a first logic circuit, a second logic circuit, and a transmission gate. The first logic circuit is configured to receive an inverted first input signal and a second input signal and generates a first output signal. The second logic circuit is configured to receive a first input signal and the second input signal and generates a second output signal. The transmission gate is configured to receive the first output signal and generates a control signal to at least one power transistor coupled between the power management circuit and the memory device. During a standby mode, the power transistor is turned on to make a first voltage equal to a predetermined voltage and during a sleep mode, the control signal is coupled to a first voltage. The predetermined voltage is greater than the first voltage.
    Type: Application
    Filed: June 22, 2020
    Publication date: April 29, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Chen Kuo, Cheng-Hung Lee, Chi-Ting Cheng, Hua-Hsin Yu, Wei-Jer Hsieh, Yu-Hao Hsu, Yang-Syu Lin, Che-Ju Yeh
  • Patent number: 10964355
    Abstract: A device includes a memory array. The memory array includes a first sub-bank, a first strap cell coupled to the first sub-bank, and a first continuous data line. The first continuous data line includes a first portion and a second portion coupled to the first sub-bank via the first strap cell. The first portion of the first continuous data line is disposed above the first strap cell and the second portion of the first continuous data line is disposed above the first portion of the first continuous data line.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung Chang, Cheng-Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon-Jhy Liaw, Yen-Huei Chen
  • Publication number: 20200152242
    Abstract: A device includes a memory array. The memory array includes a first sub-bank, a first strap cell coupled to the first sub-bank, and a first continuous data line. The first continuous data line includes a first portion and a second portion coupled to the first sub-bank via the first strap cell. The first portion of the first continuous data line is disposed above the first strap cell and the second portion of the first continuous data line is disposed above the first portion of the first continuous data line.
    Type: Application
    Filed: January 15, 2020
    Publication date: May 14, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung CHANG, Cheng-Hung LEE, Chi-Ting CHENG, Hung-Jen LIAO, Jhon-Jhy LIAW, Yen-Huei CHEN
  • Patent number: 10541007
    Abstract: A device includes a memory array. The memory array includes a first sub-bank, a second sub-bank, a strap cell and a continuous data line. The strap cell is arranged between the first sub-bank and the second sub-bank. The continuous data line includes a first portion coupled to the first sub-bank and a second portion disposed across the second sub-bank. The first portion of the continuous data line and the second portion of the continuous data line are disposed at separate layers above the strap cell.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: January 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung Chang, Cheng-Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon-Jhy Liaw, Yen-Huei Chen
  • Publication number: 20190172501
    Abstract: A device includes a memory array. The memory array includes a first sub-bank, a second sub-bank, a strap cell and a continuous data line. The strap cell is arranged between the first sub-bank and the second sub-bank. The continuous data line includes a first portion coupled to the first sub-bank and a second portion disposed across the second sub-bank. The first portion of the continuous data line and the second portion of the continuous data line are disposed at separate layers above the strap cell.
    Type: Application
    Filed: February 1, 2019
    Publication date: June 6, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung CHANG, Cheng-Hung LEE, Chi-Ting CHENG, Hung-Jen LIAO, Jhon-Jhy LIAW, Yen-Huei CHEN
  • Patent number: 10204660
    Abstract: A device includes a memory array including a first sub-bank, a second sub-bank, a first strap cell and a data line. The first strap cell is arranged between the first sub-bank and the second sub-bank. The data line includes a first portion and a second portion. The first portion is arranged across the first sub-bank. The second portion is arranged across the second sub-bank, and is coupled to the first portion via the first strap cell.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: February 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung Chang, Cheng-Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon-Jhy Liaw, Yen-Huei Chen
  • Publication number: 20180096710
    Abstract: A device includes a memory array including a first sub-bank, a second sub-bank, a first strap cell and a data line. The first strap cell is arranged between the first sub-bank and the second sub-bank. The data line includes a first portion and a second portion. The first portion is arranged across the first sub-bank. The second portion is arranged across the second sub-bank, and is coupled to the first portion via the first strap cell.
    Type: Application
    Filed: December 4, 2017
    Publication date: April 5, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung Chang, Cheng-Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon-Jhy Liaw, Yen-Huei Chen
  • Patent number: 9842627
    Abstract: A device includes a first strap cell, a first data line, and a second data line. The first strap cell is arranged between a first row of memory cells and a second row of memory cells in a memory array. A first portion of the first data line is configured to transmit data to or from a first memory cell in the first row of memory cells. The second data line and a second portion of the first data line are configured to transmit data to or from a second memory cell in the second row of memory cells.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: December 12, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung Chang, Cheng-Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon-Jhy Liaw, Yen-Huei Chen
  • Publication number: 20170162232
    Abstract: A device includes a first strap cell, a first data line, and a second data line. The first strap cell is arranged between a first row of memory cells and a second row of memory cells in a memory array. A first portion of the first data line is configured to transmit data to or from a first memory cell in the first row of memory cells. The second data line and a second portion of the first data line are configured to transmit data to or from a second memory cell in the second row of memory cells.
    Type: Application
    Filed: February 21, 2017
    Publication date: June 8, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung CHANG, Cheng-Hung LEE, Chi-Ting CHENG, Hung-Jen LIAO, Jhon-Jhy LIAW, Yen-Huei CHEN
  • Patent number: 9601162
    Abstract: A device includes a memory array, a first data line, and a second data line. The memory array includes a first strap cell, a first sub-bank, and a second sub-bank, in which the first strap cell is disposed between the first sub-bank and the second sub-bank. The first data line has a first portion and a second portion, in which the first portion of the first data line is disconnected from the second portion of the first data line, and the second portion of the first data line is configured to couple the first sub-bank to a first input/output (I/O) circuit. The second data line and the first portion of the first data line are configured to couple the second sub-bank to the first I/O circuit.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: March 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung Chang, Cheng-Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon-Jhy Liaw, Yen-Huei Chen