Abstract: In memory array of a memory circuit, a discharging module and an auxiliary module are disposed on each column line. While accessing an objective memory unit on a column line of the memory, the memory unit discharges the corresponding row line of the objective memory unit according to a discharging signal and a column selective signal. When the objective memory unit is enabled, the voltage level of the corresponding column line is changed, if the voltage level reaches a threshold voltage level, the auxiliary module enhances the increment of the voltage level of the column line.

Abstract: In a memory circuit, memory cells are arranged in a matrix by “row line-and column line” (may also denoted as “word line and bit line”). The invention provides a memory circuit and related method capable for independently pre-charging the column lines or bit lines selectively during data accessing according to results of column pre-decoding to decrease the pre-charging power consumption. After pre-charging, the objective memory cell is enabled to change or not to change the corresponding electric level of the connected column line according to the stored data, and a sense amplifier detects the stored data by measuring the electric level of the column line.

Abstract: In memory array of a memory circuit, a discharging module and an auxiliary module are disposed on each column line. While accessing an objective memory unit on a column line of the memory, the memory unit discharges the corresponding row line of the objective memory unit according to a discharging signal and a column selective signal. When the objective memory unit is enabled, the voltage level of the corresponding column line is changed, if the voltage level reaches a threshold voltage level, the auxiliary module enhances the increment of the voltage level of the column line.

Abstract: A gate clock circuit and related method for generating a gate clock signal according to a clock and an enable signal. The gate clock circuit includes a transmission unit for receiving an enable signal and a clock signal, a latch unit connected to the transmission unit for generating a latch signal, and an operation unit for processing a logic operation on the clock signal and the latch signal to generate a gate clock signal.

Abstract: In a memory circuit, memory cells are arranged in a matrix by “row line-and column line” (may also denoted as “word line and bit line”). The invention provides a memory circuit and related method capable for independently pre-charging the column lines or bit lines selectively during data accessing according to results of column pre-decoding to decrease the pre-charging power consumption. After pre-charging, the objective memory cell is enabled to change or not to change the corresponding electric level of the connected column line according to the stored data, and a sense amplifier detects the stored data by measuring the electric level of the column line.