Patents by Inventor Chi-Wei Chang
Chi-Wei Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11964881Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.Type: GrantFiled: July 27, 2020Date of Patent: April 23, 2024Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Pu-Wei Wu, Yi-Chieh Hsieh, Han-Yi Wang, Kuang-Chih Tso, Tzu-Ying Chan, Chung-Kai Chang, Chi-Shih Chen, Yu-Ting Cheng
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Publication number: 20240120239Abstract: A method for modulating a threshold voltage of a device. The method includes providing a fin extending from a substrate, where the fin includes a plurality of semiconductor channel layers defining a channel region for a P-type transistor. In some embodiments, the method further includes forming a first gate dielectric layer surrounding at least three sides of each of the plurality of semiconductor channel layers of the P-type transistor. Thereafter, the method further includes forming a P-type metal film surrounding the first gate dielectric layer. In an example, and after forming the P-type metal film, the method further includes annealing the semiconductor device. After the annealing, and in some embodiments, the method includes removing the P-type metal film.Type: ApplicationFiled: March 10, 2023Publication date: April 11, 2024Inventors: Cheng-Wei CHANG, Chi-Yu CHOU, Lun-Kuang TAN, Shuen-Shin LIANG
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Patent number: 11955397Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.Type: GrantFiled: November 9, 2020Date of Patent: April 9, 2024Assignee: Vanguard International Semiconductor CorporationInventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
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Publication number: 20240112688Abstract: The present disclosure provides an audio compression device, an audio compressing system and an audio compression method. The audio compression device comprises a first transceiver and a first processor. The first transceiver is connected to the first processor. The processor obtains an audio signal and an available bandwidth, and the processor performs an audio compression encoding on the audio signal to obtain a sample audio signal, and then compares with the audio signal and the sample audio signal to generate a residual signal, and the residual signal is transmitted according to the available bandwidth. The audio signal can be completely transmitted to an audio decompression device to reduce the distortion of the audio signal.Type: ApplicationFiled: October 4, 2022Publication date: April 4, 2024Applicant: SAVITECH CORP.Inventors: Sing-Ban Robert TIEN, Wen-Wei KANG, Wu-Lin CHANG, Chi-Feng HUANG, Lee-Chang PANG
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Publication number: 20240105787Abstract: Embodiments of the present disclosure provide a method of forming a contact opening using selective ALE operations to remove ILD layer along an upper profile of a source/drain region, and then form a source/drain contact feature having a concave bottom profile with increased contact area.Type: ApplicationFiled: February 1, 2023Publication date: March 28, 2024Inventors: Cheng-Wei CHANG, Shahaji B. MORE, Chi-Yu CHOU, Yueh-Ching PAI
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Publication number: 20240096756Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.Type: ApplicationFiled: November 22, 2023Publication date: March 21, 2024Inventors: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Syuan CIOU, Hui-Zhong ZHUANG, Ching-Wei TSAI, Shang-Wen CHANG
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Publication number: 20240088023Abstract: An interconnect structure includes a dielectric layer, a first conductive feature, a hard mask layer, a conductive layer, and a capping layer. The first conductive feature is disposed in the dielectric layer. The hard mask layer is disposed on the first conductive feature. The conductive layer includes a first portion and a second portion, the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer. The hard mask layer and the conductive layer are formed by different materials. The capping layer is disposed on the dielectric layer and the conductive layer.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Inventors: Shao-Kuan LEE, Kuang-Wei YANG, Cherng-Shiaw TSAI, Cheng-Chin LEE, Ting-Ya LO, Chi-Lin TENG, Hsin-Yen HUANG, Hsiao-Kang CHANG, Shau-Lin SHUE
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Patent number: 11929016Abstract: A scan-type display apparatus includes an LED array and a scan driver. The LED array has a common anode configuration, and includes multiple scan lines, multiple data lines and multiple LEDs. The scan driver includes multiple scan driving circuits. Each scan driving circuit includes a voltage generator and a detector. The voltage generator has an output terminal that is connected to the scan line corresponding to the scan driving circuit, and is configured to output one of an input voltage and a clamp voltage at the output terminal of the voltage generator. The detector is connected to the output terminal of the voltage generator, and generates a detection signal that indicates whether any one of the LEDs connected to the scan line corresponding to the scan driving circuit is short circuited based on a voltage at the output terminal of the voltage generator and a detection timing signal.Type: GrantFiled: December 5, 2022Date of Patent: March 12, 2024Assignee: MACROBLOCK, INC.Inventors: Chi-Min Hsieh, Che-Wei Chang, Chen-Yuan Kuo, Wei-Hsiang Cheng
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Publication number: 20230021921Abstract: Embodiments of the present disclosure relate to an apparatus and methods for preparing alcoholic beverages. In some embodiments, the apparatus includes a container, a sealing device, a first chamber, a second chamber disposed over the first chamber, and a plate disposed between the first and second chambers. The container, the sealing device, and the first chamber are sealingly connected, and the first chamber, the plate, and the second chamber are sealingly connected. The components form a closed system for an alcohol vapor to travel from the container to the second chamber without the risk of leaking out of the system.Type: ApplicationFiled: July 23, 2021Publication date: January 26, 2023Inventor: Joseph Chi-Wei CHANG
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Publication number: 20210238798Abstract: The present disclosure provides an artificial leather including a fabric layer and an ethylene-propylene copolymer (EPM) layer attached to the fabric layer. The EPM layer is an EPM composite layer including an EPM foaming layer and an EPM surface layer. The present disclosure further provides a method for manufacturing the artificial leather, and a shoe structure including the artificial leather.Type: ApplicationFiled: January 27, 2021Publication date: August 5, 2021Inventors: CHIH-YI LIN, KUO-KUANG CHENG, CHI-CHIN CHIANG, CHI-WEI CHANG
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Patent number: 11042982Abstract: An ultra-dense electrode-based brain imaging system with high spatial and temporal resolution. A Sparsity and Smoothness enhanced Method Of Optimized electrical TomograpHy (s-SMOOTH) based reconstruction technique to improve the spatial resolution and localization accuracy of reconstructed brain images is described. Also described is a graph Fractional-Order Total Variation (gFOTV) based reconstruction technique to improve the spatial resolution and localization accuracy of reconstructed brain images.Type: GrantFiled: March 5, 2018Date of Patent: June 22, 2021Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Wentai Liu, Ying Li, Jing Qin, Chi-Wei Chang, Yi-Kai Lo
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Patent number: 10515813Abstract: Embodiments of mechanisms of an etching apparatus are provided. The etching apparatus includes a processing chamber. The etching apparatus also includes a gas distribution plate disposed in the processing chamber and comprising a number of exhaust openings. The etching apparatus further includes a number of end-point detectors disposed on the gas distribution plate. The gas distribution plate is configured to spurt gas into the processing chamber via the exhaust openings during a semiconductor process.Type: GrantFiled: December 10, 2013Date of Patent: December 24, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Wei Chang, Ping-Ling Fan
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Publication number: 20180276822Abstract: An ultra-dense electrode-based brain imaging system with high spatial and temporal resolution. A Sparsity and Smoothness enhanced Method Of Optimized electrical TomograpHy (s-SMOOTH) based reconstruction technique to improve the spatial resolution and localization accuracy of reconstructed brain images is described. Also described is a graph Fractional-Order Total Variation (gFOTV) based reconstruction technique to improve the spatial resolution and localization accuracy of reconstructed brain images.Type: ApplicationFiled: March 5, 2018Publication date: September 27, 2018Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Wentai Liu, Ying Li, Jing Qin, Chi-Wei Chang, Yi-Kai Lo
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Patent number: 10057674Abstract: A headphone system includes a headphone body and a signal source device. The headphone body includes a connection kit, a first earmuff module, a second earmuff module, a connection port, and a processor. The first earmuff module is connected to a first terminal of the connection kit. The first earmuff module includes at least one first pressure sensor and a first speaker. The second earmuff module is connected to a second terminal of the connection kit. The second earmuff module includes at least one second pressure sensor and a second speaker. The connection port is used for receiving an audio source signal from the signal source device. The processor receives a plurality of pressure values detected by the at least one first pressure sensor and second pressure sensor and sets at least one set of equalizer gains of the first speaker and the second speaker according to the pressure values.Type: GrantFiled: November 6, 2017Date of Patent: August 21, 2018Assignee: Toong In Electronic Corp.Inventors: Teng-Sung Tseng, Chi-Wei Chang
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Patent number: 9658316Abstract: In accordance with some embodiments, a positioning calibration device arranged within a transfer buffer is provided. The positioning calibration device includes at least one target element and at least three positioning modules. The at least one target element is arranged on a wafer transportation apparatus within the transfer buffer. The transportation apparatus is utilized to transfer a wafer. The at least three positioning modules are utilized to detect the positions of the at least one target element by wireless communications for generating position information of the wafer transportation apparatus. The heights which each of the at least three positioning modules arranged at are not the same.Type: GrantFiled: December 30, 2013Date of Patent: May 23, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Wei Chang, Woo-Guan Chiong
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Patent number: 9373300Abstract: A power management method and a power management device for a display are disclosed, including: comparing contents in an original frame image with contents in a previous image to generate a plurality of successive second periods with first stages and second stages, shortening a plurality of time intervals in the first pulse timing distribution and outputting the first pulse timing distribution for displaying a first sub-frame image on the display during the first stage of one of the plurality of successive second periods, and shortening a plurality of time intervals in the second pulse timing distribution and outputting the second pulse timing distribution for displaying a second sub-frame image on the display during the first stage of the other one of the plurality of successive second periods; and turning off the driving circuit of the display in the second stages.Type: GrantFiled: December 26, 2014Date of Patent: June 21, 2016Assignee: AU OPTRONICS CORP.Inventors: Chi-Wei Chang, Feng-Ming Hsu, Szu-Che Yeh
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Publication number: 20160118012Abstract: A power management method and a power management device for a display are disclosed, including: comparing contents in an original frame image with contents in a previous image to generate a plurality of successive second periods with first stages and second stages, shortening a plurality of time intervals in the first pulse timing distribution and outputting the first pulse timing distribution for displaying a first sub-frame image on the display during the first stage of one of the plurality of successive second periods, and shortening a plurality of time intervals in the second pulse timing distribution and outputting the second pulse timing distribution for displaying a second sub-frame image on the display during the first stage of the other one of the plurality of successive second periods; and turning off the driving circuit of the display in the second stages.Type: ApplicationFiled: December 26, 2014Publication date: April 28, 2016Inventors: Chi-Wei Chang, Feng-Ming Hsu, Szu-Che Yeh
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Publication number: 20150185310Abstract: In accordance with some embodiments, a positioning calibration device arranged within a transfer buffer is provided. The positioning calibration device includes at least one target element and at least three positioning modules. The at least one target element is arranged on a wafer transportation apparatus within the transfer buffer. The transportation apparatus is utilized to transfer a wafer. The at least three positioning modules are utilized to detect the positions of the at least one target element by wireless communications for generating position information of the wafer transportation apparatus. The heights which each of the at least three positioning modules arranged at are not the same.Type: ApplicationFiled: December 30, 2013Publication date: July 2, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Wei CHANG, Woo-Guan CHIONG
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Publication number: 20150162227Abstract: Embodiments of mechanisms of an etching apparatus are provided. The etching apparatus includes a processing chamber. The etching apparatus also includes a gas distribution plate disposed in the processing chamber and comprising a number of exhaust openings. The etching apparatus further includes a number of end-point detectors disposed on the gas distribution plate. The gas distribution plate is configured to spurt gas into the processing chamber via the exhaust openings during a semiconductor process.Type: ApplicationFiled: December 10, 2013Publication date: June 11, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Wei CHANG, Ping-Ling FAN
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Patent number: 8292440Abstract: A projection module includes a base, a light source, a light valve, a lens module, and an adjustment module. The light source is disposed on the base and capable of providing an illumination beam. The light valve is disposed on the base and capable of converting the illumination beam into an image beam. The lens module is slidably disposed on the base and capable of projecting the image beam. The adjustment mechanism includes a rolling wheel and a slide pin. The rolling wheel is pivotably mounted to the base and includes a slide groove. The slide pin is fixed to the lens module and extends into the slide groove. The rolling wheel is capable of pivoting to drive the slide groove to pivot and the slide groove moves the slide pin to drive the lens module to move with respect to the base when the slide groove pivots.Type: GrantFiled: August 5, 2010Date of Patent: October 23, 2012Assignee: Young Optics Inc.Inventors: Chi-Wei Chang, Wei-Szu Lin, Hsu-Chun Cheng