Patents by Inventor Chi-Yang Yu
Chi-Yang Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220301889Abstract: Integrated circuit packages and methods of forming the same are disclosed. A first die is mounted on a first side of a workpiece, the workpiece including a second die. The workpiece is mounted to a front side of a package substrate, where the first die is at least partially disposed in a through hole in the package substrate. A heat dissipation feature may be attached on a second side of the workpiece. An encapsulant may be formed on the front side of the package substrate around the workpiece.Type: ApplicationFiled: June 10, 2022Publication date: September 22, 2022Inventors: Chen-Hua Yu, Chien-Hsun Lee, Chi-Yang Yu, Jung Wei Cheng, Chin-Liang Chen
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Publication number: 20220270987Abstract: A semiconductor package includes a substrate, a semiconductor device, and a ring structure. The semiconductor device disposed on the substrate. The ring structure disposed on the substrate and surrounds the semiconductor device. The ring structure includes a first portion and a second portion. The first portion bonded to the substrate. The second portion connects to the first portion. A cavity is between the second portion and the substrate.Type: ApplicationFiled: February 25, 2021Publication date: August 25, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Jung-Wei Cheng, Yu-Min Liang, Jiun-Yi Wu, Yen-Fu Su, Chien-Chang Lin, Hsin-Yu Pan
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Publication number: 20220270994Abstract: An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.Type: ApplicationFiled: May 11, 2022Publication date: August 25, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Hai-Ming Chen, Kuan-Lin Ho, Yu-Min Liang
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Patent number: 11424220Abstract: A method of manufacturing a semiconductor structure includes providing a substrate including a redistribution layer (RDL) disposed over the substrate, disposing a first patterned mask over the RDL, disposing a first conductive material over the RDL exposed from the first patterned mask to form a first conductive pillar, removing the first patterned mask, disposing a second patterned mask over the RDL, disposing a second conductive material over the RDL exposed from the second patterned mask to form a second conductive pillar, removing the second patterned mask, disposing a first die over the first conductive pillar, and disposing a second die over the second conductive pillar. A height of the second conductive pillar is substantially greater than a height of the first conductive pillar.Type: GrantFiled: September 30, 2020Date of Patent: August 23, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chi-Yang Yu, Kuan-Lin Ho, Chin-Liang Chen, Yu-Min Liang
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Publication number: 20220246513Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a first under-bump metallization (UBM) pattern, a first conductive via, and a first dielectric layer laterally covering the first UBM pattern and the first conductive via. Entireties of a top surface and a bottom surface of the first UBM pattern are substantially planar. The first conductive via landing on the top surface of the first UBM pattern includes a vertical sidewall and a top surface connected to the vertical sidewall, and a planarized mark is on the top surface of the first conductive via. A bottom surface of the first dielectric layer is substantially flush with the bottom surface of the first UBM, and a top surface of the first dielectric layer is substantially flush with the top surface of the first conductive via.Type: ApplicationFiled: April 20, 2022Publication date: August 4, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Lin Ho, Chin-Liang Chen, Jiun-Yi Wu, Chi-Yang Yu, Yu-Min Liang, Wei-Yu Chen
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Patent number: 11387118Abstract: Integrated circuit packages and methods of forming the same are disclosed. A first die is mounted on a first side of a workpiece, the workpiece including a second die. The workpiece is mounted to a front side of a package substrate, where the first die is at least partially disposed in a through hole in the package substrate. A heat dissipation feature may be attached on a second side of the workpiece. An encapsulant may be formed on the front side of the package substrate around the workpiece.Type: GrantFiled: November 26, 2018Date of Patent: July 12, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chien-Hsun Lee, Chi-Yang Yu, Jung Wei Cheng, Chin-Liang Chen
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Patent number: 11355461Abstract: An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.Type: GrantFiled: June 29, 2020Date of Patent: June 7, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Hai-Ming Chen, Kuan-Lin Ho, Yu-Min Liang
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Patent number: 11315862Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first under-bump metallization (UBM) pattern covered by a first dielectric layer, and the first UBM pattern includes a surface substantially leveled with a surface of the first dielectric layer. The circuit substrate is electrically coupled to the redistribution structure through a conductive joint disposed on the surface of the first UBM pattern. The insulating encapsulation is disposed on the redistribution structure to cover the circuit substrate.Type: GrantFiled: June 29, 2020Date of Patent: April 26, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Lin Ho, Chin-Liang Chen, Jiun-Yi Wu, Chi-Yang Yu, Yu-Min Liang, Wei-Yu Chen
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Patent number: 11264304Abstract: A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a semiconductor substrate having a plurality of dies thereon; dispensing an underfill material and a molding compound to fill spaces beneath and between the dies; disposing a temporary carrier over the dies; thinning a thickness of the semiconductor substrate; performing back side metallization upon the thinned semiconductor substrate; removing the temporary carrier; and attaching a plate over the dies. An associated semiconductor structure is also disclosed.Type: GrantFiled: March 17, 2020Date of Patent: March 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Liang Chen, Chi-Yang Yu, Kuan-Lin Ho, Yu-Min Liang
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Patent number: 11244879Abstract: A semiconductor package including a first semiconductor device, a second semiconductor device, an insulating encapsulant, a redistribution structure and a supporting element is provided. The insulating encapsulant encapsulates the first semiconductor device and the second semiconductor device. The redistribution structure is over the first semiconductor device, the second semiconductor device and the insulating encapsulant. The redistribution structure is electrically connected to the first semiconductor device and the second semiconductor device. The supporting element is embedded in one of the insulating encapsulant and the redistribution structure.Type: GrantFiled: January 20, 2020Date of Patent: February 8, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Chien-Hsun Lee, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Min Liang
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Patent number: 11145639Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor device, at least one second semiconductor device, at least one dummy die, an encapsulant and a redistribution structure. The first semiconductor device, the at least one second semiconductor device and at least one dummy die are laterally separated from one another, and laterally encapsulated by the encapsulant. A Young's modulus of the at least one dummy die is greater than a Young's modulus of the encapsulant. A sidewall of the at least one dummy die is substantially coplanar with a sidewall of the encapsulant. The redistribution structure is disposed over the encapsulant, and electrically connected to the first semiconductor device and the at least one second semiconductor device.Type: GrantFiled: December 17, 2019Date of Patent: October 12, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Wei Cheng, Chien-Hsun Lee, Chi-Yang Yu, Hao-Cheng Hou, Hsin-Yu Pan, Tsung-Ding Wang
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Patent number: 11127644Abstract: An embodiment method includes encapsulating a semiconductor die in an encapsulant, planarizing the encapsulant, and depositing a polymer material on the encapsulant. The method further includes planarizing the polymer material and forming a metallization pattern on the polymer material. The metallization pattern electrically connects a die connector of the semiconductor die to a conductive feature disposed outside of the semiconductor die.Type: GrantFiled: September 13, 2019Date of Patent: September 21, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Hai-Ming Chen, Yu-Min Liang, Jung Wei Cheng, Chien-Hsun Lee
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Publication number: 20210242119Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a redistribution structure, a circuit substrate, and an insulating encapsulation. The redistribution structure includes a first under-bump metallization (UBM) pattern covered by a first dielectric layer, and the first UBM pattern includes a surface substantially leveled with a surface of the first dielectric layer. The circuit substrate is electrically coupled to the redistribution structure through a conductive joint disposed on the surface of the first UBM pattern. The insulating encapsulation is disposed on the redistribution structure to cover the circuit substrate.Type: ApplicationFiled: June 29, 2020Publication date: August 5, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuan-Lin Ho, Chin-Liang Chen, Jiun-Yi Wu, Chi-Yang Yu, Yu-Min Liang, Wei-Yu Chen
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Publication number: 20210210464Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die and a second die, a first encapsulant, a second encapsulant and a RDL structure. The first die includes a first connector and a first protection layer covering sidewalls of the first connector, and the second die includes a second connector. The first encapsulant is at least disposed laterally between the first die and the second die to encapsulate first sidewalls of the first die and the second die that faces each other. The second encapsulant encapsulates second sidewalls of the first die and the second die. The RDL structure is disposed on and electrically connected to the first die and the second die. The top surfaces of the first protection layer, the first encapsulant, and the second encapsulant are in contact with a bottom surface of the RDL structure.Type: ApplicationFiled: March 22, 2021Publication date: July 8, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Chien-Hsun Lee, Kuan-Lin Ho, Yu-Min Liang
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Publication number: 20210183844Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor device, at least one second semiconductor device, at least one dummy die, an encapsulant and a redistribution structure. The first semiconductor device, the at least one second semiconductor device and at least one dummy die are laterally separated from one another, and laterally encapsulated by the encapsulant. A Young's modulus of the at least one dummy die is greater than a Young's modulus of the encapsulant. A sidewall of the at least one dummy die is substantially coplanar with a sidewall of the encapsulant. The redistribution structure is disposed over the encapsulant, and electrically connected to the first semiconductor device and the at least one second semiconductor device.Type: ApplicationFiled: December 17, 2019Publication date: June 17, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jung-Wei Cheng, Chien-Hsun Lee, Chi-Yang Yu, Hao-Cheng Hou, Hsin-Yu Pan, Tsung-Ding Wang
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Patent number: 11011431Abstract: A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface, a sidewall substantially orthogonal to the first surface and the second surface; and a metallic layer surrounding and connected with the sidewall of the substrate, wherein the metallic layer includes an exposed surface substantially level with the first or second surface of the substrate. Further, a method of manufacturing the semiconductor structure is also disclosed.Type: GrantFiled: September 12, 2020Date of Patent: May 18, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chi-Yang Yu, Chien-Kuo Chang, Chih-Hao Lin, Jung Tsung Cheng, Kuan-Lin Ho
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Publication number: 20210098325Abstract: A semiconductor package including a first semiconductor device, a second semiconductor device, an insulating encapsulant, a redistribution structure and a supporting element is provided. The insulating encapsulant encapsulates the first semiconductor device and the second semiconductor device. The redistribution structure is over the first semiconductor device, the second semiconductor device and the insulating encapsulant. The redistribution structure is electrically connected to the first semiconductor device and the second semiconductor device. The supporting element is embedded in one of the insulating encapsulant and the redistribution structure.Type: ApplicationFiled: January 20, 2020Publication date: April 1, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Yang Yu, Chien-Hsun Lee, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Min Liang
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Patent number: 10957672Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, a second encapsulant, and a plurality of conductive terminals. The first encapsulant is at least disposed between the first die and the second die, and on the second die. The second encapsulant is aside the first die and the second die. The conductive terminals are electrically connected to the first die and the second die through a redistribution layer (RDL) structure. An interface is existed between the first encapsulant and the second encapsulant.Type: GrantFiled: December 8, 2017Date of Patent: March 23, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yang Yu, Chin-Liang Chen, Chien-Hsun Lee, Kuan-Lin Ho, Yu-Min Liang
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Publication number: 20210020606Abstract: A method of manufacturing a semiconductor structure includes providing a substrate including a redistribution layer (RDL) disposed over the substrate, disposing a first patterned mask over the RDL, disposing a first conductive material over the RDL exposed from the first patterned mask to form a first conductive pillar, removing the first patterned mask, disposing a second patterned mask over the RDL, disposing a second conductive material over the RDL exposed from the second patterned mask to form a second conductive pillar, removing the second patterned mask, disposing a first die over the first conductive pillar, and disposing a second die over the second conductive pillar. A height of the second conductive pillar is substantially greater than a height of the first conductive pillar.Type: ApplicationFiled: September 30, 2020Publication date: January 21, 2021Inventors: CHI-YANG YU, KUAN-LIN HO, CHIN-LIANG CHEN, YU-MIN LIANG
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Publication number: 20200411385Abstract: A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface, a sidewall substantially orthogonal to the first surface and the second surface; and a metallic layer surrounding and connected with the sidewall of the substrate, wherein the metallic layer includes an exposed surface substantially level with the first or second surface of the substrate. Further, a method of manufacturing the semiconductor structure is also disclosed.Type: ApplicationFiled: September 12, 2020Publication date: December 31, 2020Inventors: CHI-YANG YU, CHIEN-KUO CHANG, CHIH-HAO LIN, JUNG TSUNG CHENG, KUAN-LIN HO