Patents by Inventor Chi-yuan Shih
Chi-yuan Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9048317Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface; a fin structure extending upward from the substrate major surface, wherein the fin structure comprises a first fin, a second fin, and a third fin between the first fin and second fin; a first germanide over the first fin, wherein a first bottom surface of the first germanide has a first acute angle to the major surface; a second germanide over the second fin on a side of the third fin opposite to first germanide substantially mirror-symmetrical to each other; and a third germanide over the third fin, wherein a third bottom surface of the third germanide has a third acute angle to the major surface less than the first acute angle.Type: GrantFiled: July 31, 2013Date of Patent: June 2, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Wen Liu, Chi-Yuan Shih, Li-Chi Yu, Meng-Chun Chang, Ting-Chu Ko, Chung-Hsien Chen
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Patent number: 9041158Abstract: A semiconductor apparatus includes fin field-effect transistor (FinFETs) having controlled fin heights. The apparatus includes a high fin density area and a low fin density area. Each fin density area includes fins and dielectric material between the fins. The dielectric material includes different dopant concentrations for different fin density areas and is the same material as deposited.Type: GrantFiled: February 23, 2012Date of Patent: May 26, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Yuan-Fu Shao, Wen-Huei Guo, Tung Ying Lee
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Publication number: 20150132912Abstract: A method of fabricating a Fin field effect transistor (FinFET) includes providing a substrate having a first fin and a second fin extending above a substrate top surface, wherein the first fin has a top surface and sidewalls and the second fin has a top surface and sidewalls. The method includes forming an insulation layer between the first and second fins. The method includes forming a first gate dielectric having a first thickness covering the top surface and sidewalls of the first fin using a plasma doping process. The method includes forming a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness. The method includes forming a conductive gate strip traversing over both the first gate dielectric and the second gate dielectric.Type: ApplicationFiled: January 26, 2015Publication date: May 14, 2015Inventors: Clement Hsingjen WANN, Ling-Yen YEH, Chi-Yuan SHIH, Yi-Tang LIN, Chih-Sheng CHANG
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Publication number: 20150132911Abstract: A method of forming a fin field-effect transistor (FinFET) includes forming a plurality of fins on a substrate. The method further includes forming an oxide layer on the substrate, wherein a bottom portion of each fin of the plurality of fins is embedded in the oxide layer, and the bottom portion of each fin of the plurality of fins has substantially a same shape. The method further includes shaping at least one fin of the plurality of fins, wherein a top portion of the at least one fin has a different shape from a top portion of another fin of the plurality of fins.Type: ApplicationFiled: January 16, 2015Publication date: May 14, 2015Inventors: Clement Hsingjen WANN, Ling-Yen YEH, Chi-Yuan SHIH, Yi-Tang LIN, Chih-Sheng CHANG, Chi-Wen LIU
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Publication number: 20150102386Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.Type: ApplicationFiled: October 10, 2013Publication date: April 16, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Yu Chen, Chi-Yuan Shih, Chi-Wen Liu
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Publication number: 20150097239Abstract: A FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower fin portion comprising a first semiconductor material having a first lattice constant; an upper fin portion comprising a second semiconductor material having a second lattice constant greater than the first lattice constant; a middle fin portion comprising a third semiconductor material having a third lattice constant between the first lattice constant and the second lattice constant; and a passivation structure surrounding the fin structure comprising a lower passivation portion surrounding the lower fin portion comprising a first oxynitride of the first semiconductor material; an upper passivation portion surrounding the upper fin portion comprising a second oxynitride of the second semiconductor material; and a middle passivation portion surrounding the middle fin portion comprising a third oxynitride of the third semiconductor material.Type: ApplicationFiled: October 7, 2013Publication date: April 9, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Yu Chen, Chi-Yuan Shih, Ling-Yen Yeh, Clement Hsingjen Wann
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Publication number: 20150076499Abstract: Disclosed herein is a method for forming a test key system for characterizing wafer processing states, the method comprising forming a plurality of shallow trench isolation structures (STIs) on a substrate of a wafer and in a scribe line of the wafer and forming a test key on the substrate of a wafer and in the scribe line of the wafer. Forming the test key comprises forming at least one test key group having a plurality of test key series, each of the plurality of test key series having a plurality of test pads, each one of the plurality of test key series having a first physical characteristic different from the first physical characteristic of other test key series the at least one first test key group.Type: ApplicationFiled: September 18, 2013Publication date: March 19, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Wei-Chun Tsai
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Patent number: 8963257Abstract: The disclosure relates to a Fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first fin and a second fin extending above the substrate top surface, wherein each of the fins has a top surface and sidewalls; an insulation layer between the first and second fins extending part way up the fins from the substrate top surface; a first gate dielectric covering the top surface and sidewalls of the first fin having a first thickness and a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness; and a conductive gate strip traversing over both the first gate dielectric and second gate dielectric.Type: GrantFiled: November 10, 2011Date of Patent: February 24, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Yi-Tang Lin, Chih-Sheng Chang
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Publication number: 20150041918Abstract: A method includes growing an epitaxy semiconductor region at a major surface of a wafer. The epitaxy semiconductor region has an upward facing facet facing upwardly and a downward facing facet facing downwardly. The method further includes forming a first metal silicide layer contacting the upward facing facet, and forming a second metal silicide layer contacting the downward facing facet. The first metal silicide layer and the second metal silicide layer comprise different metals.Type: ApplicationFiled: August 9, 2013Publication date: February 12, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Clement Hsingjen Wann, Sey-Ping Sun, Ling-Yen Yeh, Chi-Yuan Shih, Li-Chi Yu, Chun Hsiung Tsai, Chin-Hsiang Lin, Neng-Kuo Chen, Meng-Chun Chang, Ta-Chun Ma, Gin-Chen Huang, Yen-Chun Huang
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Publication number: 20150035017Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface; a fin structure extending upward from the substrate major surface, wherein the fin structure comprises a first fin, a second fin, and a third fin between the first fin and second fin; a first germanide over the first fin, wherein a first bottom surface of the first germanide has a first acute angle to the major surface; a second germanide over the second fin on a side of the third fin opposite to first germanide substantially mirror-symmetrical to each other; and a third germanide over the third fin, wherein a third bottom surface of the third germanide has a third acute angle to the major surface less than the first acute angle.Type: ApplicationFiled: July 31, 2013Publication date: February 5, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Wen Liu, Chi-Yuan Shih, Li-Chi Yu, Meng-Chun Chang, Ting-Chu Ko, Chung-Hsien Chen
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Patent number: 8946829Abstract: A semiconductor apparatus includes fin field-effect transistor (FinFETs) having shaped fins and regular fins. Shaped fins have top portions that may be smaller, larger, thinner, or shorter than top portions of regular fins. The bottom portions of shaped fins and regular fins are the same. FinFETs may have only one or more shaped fins, one or more regular fins, or a mixture of shaped fins and regular fins. A semiconductor manufacturing process to shape one fin includes forming a photolithographic opening of one fin, optionally doping a portion of the fin, and etching a portion of the fin.Type: GrantFiled: October 14, 2011Date of Patent: February 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Yi-Tang Lin, Chih-Sheng Chang, Chi-Wen Liu
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Publication number: 20150021710Abstract: A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.Type: ApplicationFiled: July 19, 2013Publication date: January 22, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Yu Hsu, Yi-Tang Lin, Clement Hsinjen Wann, Chih-Sheng Chang, Wei-Chun Tsai, Jyh-Cherng Sheu, Chi-Yuan Shih
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Publication number: 20140147943Abstract: A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at least one semiconductor fin. A resistance of the at least one semiconductor fin is calculated. A carrier concentration of the semiconductor fin is calculated from the resistance.Type: ApplicationFiled: November 29, 2012Publication date: May 29, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Clement Hsingjen Wann, Yasutoshi Okuno, Ling-Yen Yeh, Chi-Yuan Shih, Yuan-Fu Shao, Wei-Chun Tsai
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Patent number: 8721892Abstract: Systems and methods for monitoring analytes in real time using integrated chromatography systems and devices. Integrated microfluidic liquid chromatography devices and systems include multiple separation columns integrated into a single substrate. Using such a device, parallel analysis of multiple samples can be performed simultaneously and/or sequential analysis of a single sample can be performed simultaneously on a single chip or substrate. The devices and systems are well suited for use in high pressure liquid chromatography (HPLC) applications. HPLC chips and devices including embedded parylene channels can be fabricated using a single mask process.Type: GrantFiled: October 28, 2013Date of Patent: May 13, 2014Assignee: California Institute of TechnologyInventors: Chi-Yuan Shih, Yu-Chong Tai, Jun Xie, Darron K. Young, Po-Jui Chen
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Publication number: 20140048481Abstract: Systems and methods for monitoring analytes in real time using integrated chromatography systems and devices. Integrated microfluidic liquid chromatography devices and systems include multiple separation columns integrated into a single substrate. Using such a device, parallel analysis of multiple samples can be performed simultaneously and/or sequential analysis of a single sample can be performed simultaneously on a single chip or substrate. The devices and systems are well suited for use in high pressure liquid chromatography (HPLC) applications. HPLC chips and devices including embedded parylene channels can be fabricated using a single mask process.Type: ApplicationFiled: October 28, 2013Publication date: February 20, 2014Applicant: California Institute of TechnologyInventors: Chi-Yuan Shih, Yu-Chong Tai, Jun Xie, Darron K. Young, Po-Jui Chen
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Publication number: 20140042500Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a Ge-containing dielectric layer over the strained material; and a metal layer over the Ge-containing dielectric layer.Type: ApplicationFiled: August 9, 2012Publication date: February 13, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Yen-Yu Chen
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Patent number: 8605276Abstract: One of the broader forms of the present disclosure involves a method of enhanced defect inspection. The method includes providing a substrate having defect particles and providing a fluid over the substrate and the defect particles, the fluid having a refractive index greater than air. The method further includes exposing the substrate and the defect particles to incident radiation through the fluid, and detecting, through the fluid, radiation reflected or scattered by the defect particles.Type: GrantFiled: November 1, 2011Date of Patent: December 10, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Jen Wu, Chen-Ming Huang, Kuan-Chieh Huang, Chi-Yuan Shih, Chin-Hsiang Lin
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Patent number: 8592287Abstract: A method comprises providing a semiconductor substrate having a first layer and a second layer above the first layer. The first layer haw a plurality of first patterns, vias or contacts. The second layer has second patterns corresponding to the first patterns, vias or contacts. The second patterns have a plurality of in-plane offsets relative to the corresponding first patterns, vias or contacts. A scanning electron microscope is used to measure line edge roughness (LER) values of the second patterns. An overlay error is calculated between the first and second layers based on the measured LER values.Type: GrantFiled: August 2, 2011Date of Patent: November 26, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Yuan Shih, I-Hsiung Huang, Heng-Hsin Liu
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Patent number: 8574432Abstract: Systems and methods for monitoring analytes in real time using integrated chromatography systems and devices. Integrated microfluidic liquid chromatography devices and systems include multiple separation columns integrated into a single substrate. Using such a device, parallel analysis of multiple samples can be performed simultaneously and/or sequential analysis of a single sample can be performed simultaneously on a single chip or substrate. The devices and systems are well suited for use in high pressure liquid chromatography (HPLC) applications. HPLC chips and devices including embedded parylene channels can be fabricated using a single mask process.Type: GrantFiled: April 14, 2006Date of Patent: November 5, 2013Assignee: California Institute of TechnologyInventors: Chi-yuan Shih, Yu-Chong Tai, Jun Xie, Darron K. Young, Po-Jui Chen
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Publication number: 20130221491Abstract: A semiconductor apparatus includes fin field-effect transistor (FinFETs) having controlled fin heights. The apparatus includes a high fin density area and a low fin density area. Each fin density area includes fins and dielectric material between the fins. The dielectric material includes different dopant concentrations for different fin density areas and is the same material as deposited.Type: ApplicationFiled: February 23, 2012Publication date: August 29, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Yuan-Fu Shao, Wen-Huei Guo, Tung Ying Lee