Patents by Inventor Chi-Yuan Wen

Chi-Yuan Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150258937
    Abstract: device vehicle includes a pillar, a driver seat and a blind spot monitor device including a camera module, a display module and a mounting component. The camera module includes a camera disposed to substantially face a direction along a line of sight of a driver who sits in the driver seat toward the pillar and operable to capture an image of a blind spot attributed to the pillar and to output an image data signal. The display module includes a display coupled to the camera module for receiving the image data signal and operable to display the image of the blind spot according to the image data signal. The mounting component supports the display module at a position within the line of sight of the driver toward the pillar.
    Type: Application
    Filed: March 12, 2015
    Publication date: September 17, 2015
    Inventor: Chi-Yuan WEN
  • Patent number: 8293649
    Abstract: A method of forming an integrated circuit structure on a wafer includes providing an etcher having an electrostatic chuck (ESC); and placing the wafer on the ESC. The wafer includes a conductive feature and a dielectric layer over the conductive feature. The method further includes forming and patterning a photo resist over the wafer; and etching the dielectric layer to form a via opening in the wafer using the etcher. An ashing is performed to the photo resist to remove the photo resist. An oxygen neutralization is performed to the wafer. A de-chuck step is performed to release the wafer from the ESC.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: October 23, 2012
    Assignee: Global Unichip Corp.
    Inventors: Ting-Yi Lin, Chi-Yuan Wen
  • Patent number: 8263495
    Abstract: A method of forming an integrated circuit structure on a wafer includes providing a first etcher comprising a first electrostatic chuck (ESC); placing the wafer on the first ESC; and forming a via opening in the wafer using the first etcher. After the step of forming the via opening, a first reverse de-chuck voltage is applied to the first ESC to release the wafer. The method further includes placing the wafer on a second ESC of a second etcher; and performing an etching step to form an additional opening in the wafer using the second etcher. After the step of forming the additional opening, a second reverse de-chuck voltage is applied to the second ESC to release the wafer. The second reverse de-chuck voltage is different from the first reverse de-chuck voltage.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: September 11, 2012
    Assignee: Global Unichip Corp.
    Inventors: Ting-Yi Lin, Chi-Yuan Wen, Chuang Tse Chuan, Miau-Shing Tsay, Ming Li Wu
  • Publication number: 20110151669
    Abstract: A method of forming an integrated circuit structure on a wafer includes providing a first etcher comprising a first electrostatic chuck (ESC); placing the wafer on the first ESC; and forming a via opening in the wafer using the first etcher. After the step of forming the via opening, a first reverse de-chuck voltage is applied to the first ESC to release the wafer. The method further includes placing the wafer on a second ESC of a second etcher; and performing an etching step to form an additional opening in the wafer using the second etcher. After the step of forming the additional opening, a second reverse de-chuck voltage is applied to the second ESC to release the wafer. The second reverse de-chuck voltage is different from the first reverse de-chuck voltage.
    Type: Application
    Filed: December 18, 2009
    Publication date: June 23, 2011
    Inventors: Ting-Yi Lin, Chi-Yuan Wen, Chuang Tse Chuan, Miau-Shing Tsay, Ming Li Wu
  • Publication number: 20110147338
    Abstract: A method of forming an integrated circuit structure on a wafer includes providing an etcher having an electrostatic chuck (ESC); and placing the wafer on the ESC. The wafer includes a conductive feature and a dielectric layer over the conductive feature. The method further includes forming and patterning a photo resist over the wafer; and etching the dielectric layer to form a via opening in the wafer using the etcher. An ashing is performed to the photo resist to remove the photo resist. An oxygen neutralization is performed to the wafer. A de-chuck step is performed to release the wafer from the ESC.
    Type: Application
    Filed: December 18, 2009
    Publication date: June 23, 2011
    Inventors: Ting-Yi Lin, Chi-Yuan Wen