Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a gate structure on a substrate. A doped region is within the substrate. One or more dielectric materials are within a recess formed by one or more surfaces of the substrate. The doped region is laterally between the gate structure and the recess. A doped epitaxial material is within the recess and between the one or more dielectric materials and the doped region. The doped epitaxial material is asymmetric about a vertical line that extends through a lateral center of the doped epitaxial material.

Abstract: An integrated circuit structure includes a first Inter-Layer Dielectric (ILD), a gate stack in the first ILD, a second ILD over the first ILD, a contact plug in the second ILD, and a dielectric protection layer on opposite sides of, and in contact with, the contact plug. The contact plug and the dielectric protection layer are in the second ILD. A dielectric capping layer is over and in contact with the contact plug.

Abstract: Apparatus and methods for effective impurity gettering are described herein. In some embodiments, a described device includes: a substrate; a pixel region disposed in the substrate; an isolation region disposed in the substrate and within a proximity of the pixel region; and a heterogeneous layer on the seed area. The isolation region comprises a seed area including a first semiconductor material. The heterogeneous layer comprises a second semiconductor material that has a lattice constant different from that of the first semiconductor material.

Abstract: A test load circuit includes a test load, a current sensor, and comparator. The test load is connected to a voltage source of a power supply. The current sensor is configured to detect the amount of current flowing through the test load. The comparator has a first input connected to a feedback signal having a voltage associated with the test load current, a second input connected to a command signal having has a voltage associated with a target current through the test load, and an output connected to the test load. The output of the comparator has a voltage that is based on the current difference between the target current and the test load current. The test load has a variable resistance that is controllable by the output of the comparator to adjust the test load current and cause the test load current to match the target current.

Abstract: Provided herein is a modified cobalt oxide based catalyst that includes cobalt oxide and lanthanum. The lanthanum is dispersed within the cobalt oxide, wherein the lanthanum is about 5-20% by weight of the modified cobalt oxide based catalyst. The method of producing the lanthanum modified cobalt oxide based catalyst and its use in producing hydrogen are also disclosed.