Patents by Inventor Chia-Chang Hsu

Chia-Chang Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210294203
    Abstract: A lithography mask includes a substrate, a reflective structure disposed over a first side of the substrate, and a patterned absorber layer disposed over the reflective structure. The lithography mask includes a first region and a second region that surrounds the first region in a top view. The patterned absorber layer is located in the first region. A substantially non-reflective material is located in the second region. The lithography mask is formed by forming a reflective structure over a substrate, forming an absorber layer over the reflective structure, defining a first region of the lithography mask, and defining a second region of the lithography mask. The defining of the first region includes patterning the absorber layer. The second region is defined to surround the first region in a top view. The defining of the second region includes forming a substantially non-reflective material in the second region.
    Type: Application
    Filed: June 7, 2021
    Publication date: September 23, 2021
    Inventors: Chin-Hsiang Lin, Chien-Cheng Chen, Hsin-Chang Lee, Chia-Jen Chen, Pei-Cheng Hsu, Yih-Chen Su, Gaston Lee, Tran-Hui Shen
  • Patent number: 11121018
    Abstract: A reticle holding tool is provided. The reticle holding tool includes a housing, a reticle chuck, and a gas delivery assembly. The housing includes an opening, a top housing member, and a lateral housing member extending from the top housing member and terminating at a lower edge which is located on a predetermined plane. The reticle chuck is positioned in the housing and has an effective surface configured to secure a reticle. The effective surface is located between the predetermined plane and the top housing member. The reticle chuck is movable between two boundary lines that are perpendicular to the effective surface. A width of the opening is greater than a distance between the two boundary lines. The gas delivery assembly is positioned within the housing and configured to supply gas into the housing.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chueh-Chi Kuo, Tsung-Yen Lee, Chia-Hsin Chou, Tzung-Chi Fu, Li-Jui Chen, Po-Chung Cheng, Che-Chang Hsu
  • Patent number: 11121307
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a cap layer on the first MTJ and the second MTJ; forming a passivation layer on the cap layer; removing part of the passivation layer to form a recess between the first MTJ and the second MTJ; forming an anti-reflective layer on the passivation layer and filling the recess; and removing the anti-reflective layer, the passivation layer, and the cap layer to form a first contact hole.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: September 14, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Chia-Chang Hsu, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Patent number: 11118591
    Abstract: An intelligent fan with interface compatibility is provided. The intelligent fan includes a fan body having a fan and a motor, a driving circuit, a tachometer, an output connector including a first pin, a second pin, a third pin and a fourth pin connected to a fan connector of a motherboard, and a microcontroller connected to the driving circuit and the tachometer, and connected to the motherboard via the first, second, third and fourth pins. When the intelligent fan is powered on, the microcontroller sets the third and fourth pins as input pins for receiving an output signal of the fan connector of the motherboard, and the microcontroller performs an I2C signal analysis on the output signal. When the I2C signal analysis succeeds, the intelligent fan is set in an I2C mode, and when the I2C signal analysis fails, the intelligent fan is set in a PWM mode.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: September 14, 2021
    Assignee: PROLIFIC TECHNOLOGY INC.
    Inventors: Chia Chang Hsu, Chih Feng Huang, Ching Te Chen, Ren Yuan Yu
  • Patent number: 11114890
    Abstract: A DC uninterruptible power supply apparatus with bidirectional protection function receives a DC power source and supplies power to a DC load. The DC uninterruptible power supply apparatus includes a first loop, a second loop, a third loop, and a control unit. The first loop receives the DC power source and supplies power to the DC load. The second loop converts the DC power source into an energy-storing power source to charge an energy-storing unit. The energy-storing unit provides a backup power source to the DC load through the third loop and the first loop. The control unit controls the first loop, the second loop, and the third loop to correspondingly provide a first protection mechanism, a second protection mechanism, and a third protection mechanism.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: September 7, 2021
    Assignee: Delta Electronics, Inc.
    Inventors: Sheng-Jian Chen, Chia-Chang Hsu, Zong-Jin Chuang
  • Publication number: 20210272964
    Abstract: A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 2, 2021
    Inventors: Chern-Yow Hsu, Chen-Jong Wang, Chia-Shiung Tsai, Shih-Chang Liu, Xiaomeng Chen
  • Patent number: 11106000
    Abstract: A driving mechanism for supporting an optical member is provided, including a base, a frame, a movable portion, a driving module, and an adhesive member. The base includes a plurality of first sidewalls, and at least one recess is formed on the first sidewalls. The frame includes a plurality of second sidewalls, and at least one opening is formed on the second sidewalls. The base and the frame form a hollow box, and the opening corresponds to the recess. The movable portion and the driving module are disposed in the hollow box. The driving module can drive the movable portion to move relative to the base. The adhesive member is accommodated in the opening and the recess, and extended along the first sidewalls. The adhesive member is disposed between the first sidewalls and the second sidewalls.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: August 31, 2021
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Bing-Ru Song, Yi-Ho Chen, Chia-Pin Hsu, Chih-Wei Weng, Shin-Hua Chen, Chien-Lun Huang, Chao-Chun Chang, Shou-Jen Liu, Kun-Shih Lin, Nai-Wen Hsu, Yu-Cheng Lin, Shang-Yu Hsu, Yu-Huai Liao, Yi-Hsin Nieh, Shih-Ting Huang, Kuo-Chun Kao, Fu-Yuan Wu
  • Publication number: 20210184569
    Abstract: A power supply with duty cycle limiting circuit includes a conversion circuit, a drive circuit, a control unit, and a duty cycle limiting circuit. The duty cycle limiting circuit converts a control signal into a control voltage, and determines whether a power switch of a power supply is turned off according to the control voltage and a threshold voltage to limit a duty cycle of the power switch.
    Type: Application
    Filed: September 23, 2020
    Publication date: June 17, 2021
    Inventors: Ming-Wei CHOU, Sheng-Jian CHEN, Chia-Chang HSU, Cheng-Yi LO
  • Publication number: 20210175740
    Abstract: A DC uninterruptible power supply apparatus with bidirectional protection function receives a DC power source and supplies power to a DC load. The DC uninterruptible power supply apparatus includes a first loop, a second loop, a third loop, and a control unit. The first loop receives the DC power source and supplies power to the DC load. The second loop converts the DC power source into an energy-storing power source to charge an energy-storing unit. The energy-storing unit provides a backup power source to the DC load through the third loop and the first loop. The control unit controls the first loop, the second loop, and the third loop to correspondingly provide a first protection mechanism, a second protection mechanism, and a third protection mechanism.
    Type: Application
    Filed: April 17, 2020
    Publication date: June 10, 2021
    Inventors: Sheng-Jian CHEN, Chia-Chang HSU, Zong-Jin CHUANG
  • Publication number: 20210167282
    Abstract: A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.
    Type: Application
    Filed: January 19, 2021
    Publication date: June 3, 2021
    Inventors: Hui-Lin Wang, Chia-Chang Hsu, Rai-Min Huang
  • Patent number: 10998147
    Abstract: Disclosures of the present invention describe a switch device has a controlling and processing unit comprising a first zero point detector, a second zero point detector, an arc detector, and a microcontroller. According to zero crossing point of input voltage signal, zero crossing point of output voltage signal, relay's delay time, and arc-spark-induced signal, the microcontroller is capable of adaptively generating a relay controlling signal to control the relay, such that the relay achieves a short-circuit switching at the zero cross point of output voltage signal for making the output voltage signal be transmitted to at least one load device. Moreover, the microcontroller is also able to control the relay to finish a short-circuit switching at the zero cross point of input voltage signal, so as to stop the output voltage signal from being transmitted to the load device.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: May 4, 2021
    Assignee: Prolific Technology Inc.
    Inventor: Chia-Chang Hsu
  • Patent number: 10937946
    Abstract: A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: March 2, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chia-Chang Hsu, Rai-Min Huang
  • Publication number: 20210057637
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a cap layer on the first MTJ and the second MTJ; forming a passivation layer on the cap layer; removing part of the passivation layer to form a recess between the first MTJ and the second MTJ; forming an anti-reflective layer on the passivation layer and filling the recess; and removing the anti-reflective layer, the passivation layer, and the cap layer to form a first contact hole.
    Type: Application
    Filed: September 19, 2019
    Publication date: February 25, 2021
    Inventors: Chih-Wei Kuo, Chia-Chang Hsu, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Publication number: 20210036053
    Abstract: The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer.
    Type: Application
    Filed: October 20, 2020
    Publication date: February 4, 2021
    Inventors: Hui-Lin Wang, Chia-Chang Hsu, Chen-Yi Weng, Hung-Chan Lin, Jing-Yin Jhang, Yu-Ping Wang
  • Patent number: 10908189
    Abstract: Disclosures of the present invention describe a current sensing device and method, wherein the current sensing device comprises: at least one magnetic sensor, a signal receiving unit and a microprocessor. Particularly, the present invention provides an environmental magnetic field filtering unit and an effective current calculation unit in the microprocessor, such that the microprocessor is able to calculate the value of a current flowing in a specific electrical cable with high accuracy based on a sensing magnetic field outputted from the magnetic sensor.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: February 2, 2021
    Inventor: Chia-Chang Hsu
  • Publication number: 20210028351
    Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a bottom electrode layer on the IMD layer, wherein the bottom electrode layer comprises a gradient concentration; forming a free layer on the bottom electrode layer; forming a top electrode layer on the free layer; and patterning the top electrode layer, the free layer, and the bottom electrode layer to form a magnetic tunneling junction (MTJ).
    Type: Application
    Filed: October 7, 2020
    Publication date: January 28, 2021
    Inventors: Hui-Lin Wang, Chia-Chang Hsu, Chen-Yi Weng, Chin-Yang Hsieh, Jing-Yin Jhang
  • Publication number: 20210013396
    Abstract: A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.
    Type: Application
    Filed: August 15, 2019
    Publication date: January 14, 2021
    Inventors: Hui-Lin Wang, Chia-Chang Hsu, Rai-Min Huang
  • Publication number: 20200403144
    Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.
    Type: Application
    Filed: July 9, 2019
    Publication date: December 24, 2020
    Inventors: Kuo-Chih Lai, Yi-Syun Chou, Ko-Wei Lin, Pei-Hsun Kao, Wei Chen, Chia-Fu Cheng, Chun-Yao Yang, Chia-Chang Hsu
  • Patent number: 10847574
    Abstract: The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer.
    Type: Grant
    Filed: December 9, 2018
    Date of Patent: November 24, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chia-Chang Hsu, Chen-Yi Weng, Hung-Chan Lin, Jing-Yin Jhang, Yu-Ping Wang
  • Patent number: 10840432
    Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a bottom electrode layer on the IMD layer, wherein the bottom electrode layer comprises a gradient concentration; forming a free layer on the bottom electrode layer; forming a top electrode layer on the free layer; and patterning the top electrode layer, the free layer, and the bottom electrode layer to form a magnetic tunneling junction (MTJ).
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: November 17, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chia-Chang Hsu, Chen-Yi Weng, Chin-Yang Hsieh, Jing-Yin Jhang