Patents by Inventor Chia-Chang Hsu
Chia-Chang Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240122078Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.Type: ApplicationFiled: December 18, 2023Publication date: April 11, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chia-Chang Hsu, Tang-Chun Weng, Cheng-Yi Lin, Yung-Shen Chen, Chia-Hung Lin
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 11923433Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.Type: GrantFiled: March 9, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Liang Pan, Yungtzu Chen, Chung-Chieh Lee, Yung-Chang Hsu, Chia-Yang Hung, Po-Chuan Wang, Guan-Xuan Chen, Huan-Just Lin
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Publication number: 20240049608Abstract: A semiconductor device includes a substrate, a first MTJ structure, a second MTJ structure, an interconnection structure including a first metal interconnection and a second metal interconnection disposed on and contacting the first metal interconnection, a fifth metal interconnection, and a sixth metal interconnection. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction. The fifth metal interconnection and the sixth metal interconnection are disposed under and contact the first MTJ structure and the second MTJ structure, respectively. The fifth metal interconnection includes a barrier layer and a metal layer disposed on the barrier layer. A length of the first MTJ structure in the first horizontal direction is greater than a length of the metal layer in the first horizontal direction.Type: ApplicationFiled: October 18, 2023Publication date: February 8, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wei Kuo, Chia-Chang Hsu
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Patent number: 11895927Abstract: A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.Type: GrantFiled: May 13, 2021Date of Patent: February 6, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Chang Hsu, Tang-Chun Weng, Cheng-Yi Lin, Yung-Shen Chen, Chia-Hung Lin
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Patent number: 11882986Abstract: A floor types identifying device for use in a vacuum cleaner is disclosed, and comprises a current sensing unit coupled and a processing and controlling module. When a suction head is moved, a driving current of a roller brush driving motor is detected by the current sensing unit, such that the processing and controlling module judges that the suction head is moved on a specific floor that has a hard surface, a short-pile-carpeted surface or a long-pile-carpeted surface according to a variation of the driving current. Therefore, for a vacuum cleaner that is integrated with the floor types identifying device of the present invention, both suction power of the vacuum cleaner and driving power of the roller driving motor can be properly adjusted in response to the floor's surficial material type.Type: GrantFiled: March 11, 2022Date of Patent: January 30, 2024Assignee: TALENTONE HONG KONG LIMITEDInventors: Chia-Chang Hsu, Fu-Yuen Fong, Kwok Lit Chan
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Publication number: 20240032440Abstract: A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a contact plug on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.Type: ApplicationFiled: October 3, 2023Publication date: January 25, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chia-Chang Hsu, Chen-Yi Weng, Chin-Yang Hsieh, Jing-Yin Jhang
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Patent number: 11856870Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.Type: GrantFiled: June 21, 2022Date of Patent: December 26, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Chih Lai, Yi-Syun Chou, Ko-Wei Lin, Pei-Hsun Kao, Wei Chen, Chia-Fu Cheng, Chun-Yao Yang, Chia-Chang Hsu
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Publication number: 20230404346Abstract: A device for conducting motor recognition and protection is disclosed. The device comprises a current detection circuit and a microprocessor, of which the current detection circuit is used for detecting an operation current from a roller brush driving motor that is integrated in a suction head of a vacuum cleaner. Moreover, the microprocessor is configured for determining a product model of the roller brush driving motor based on the operation current, deciding a protection parameter set according to the product model, and conducting a motor protection for the roller brush driving motor after loading at least one motor protection parameter contained by the protection parameter set.Type: ApplicationFiled: May 24, 2023Publication date: December 21, 2023Applicant: PROLIFIC TECHNOLOGY INC.Inventors: CHIA-CHANG HSU, REN-YUAN YU
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Patent number: 11832527Abstract: A semiconductor device includes a substrate, a first magnetic tunnel junction (MTJ) structure, a second MTJ structure, and an interconnection structure. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction, and the interconnection structure includes a first metal interconnection and a second metal interconnection. The second metal interconnection is disposed on and contacts the first metal interconnection.Type: GrantFiled: March 27, 2022Date of Patent: November 28, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wei Kuo, Chia-Chang Hsu
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Patent number: 11818965Abstract: A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a contact plug on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.Type: GrantFiled: July 19, 2022Date of Patent: November 14, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chia-Chang Hsu, Chen-Yi Weng, Chin-Yang Hsieh, Jing-Yin Jhang
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Patent number: 11812667Abstract: A semiconductor device includes a substrate, a first magnetic tunnel junction (MTJ) structure, a second MTJ structure, and an interconnection structure. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction, and the interconnection structure includes a first metal interconnection and a second metal interconnection. The second metal interconnection is disposed on and contacts the first metal interconnection. A material composition of the second metal interconnection is different from a material composition of the first metal interconnection.Type: GrantFiled: June 7, 2021Date of Patent: November 7, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wei Kuo, Chia-Chang Hsu
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Publication number: 20230301201Abstract: A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.Type: ApplicationFiled: May 24, 2023Publication date: September 21, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wei Kuo, Chia-Chang Hsu
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Publication number: 20230262993Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.Type: ApplicationFiled: April 20, 2023Publication date: August 17, 2023Applicant: United Microelectronics Corp.Inventors: Cheng-Yi Lin, Tang Chun Weng, Chia-Chang Hsu, Yung Shen Chen, Chia-Hung Lin
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Patent number: 11706995Abstract: A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.Type: GrantFiled: February 2, 2021Date of Patent: July 18, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wei Kuo, Chia-Chang Hsu
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Patent number: 11690230Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.Type: GrantFiled: June 11, 2021Date of Patent: June 27, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Yi Lin, Tang Chun Weng, Chia-Chang Hsu, Yung Shen Chen, Chia-Hung Lin
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Patent number: 11659772Abstract: A method for forming a semiconductor structure includes the steps of providing a substrate having a device region and an alignment mark region, forming a first dielectric layer on the substrate and a second dielectric layer on the first dielectric layer, forming a conductive via in the second dielectric layer on the device region, forming a mask layer on the second dielectric layer, etching the second dielectric layer and the first dielectric layer through an opening of the mask layer on the alignment mark region to form a first trench through the second dielectric layer and an upper portion of the first dielectric layer and a plurality of second trenches in the first dielectric layer directly under the first trench. Afterward, a memory stack structure is formed on the second dielectric layer, covering the conductive via and filling into the first trench and the second trenches.Type: GrantFiled: March 28, 2022Date of Patent: May 23, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chia-Chang Hsu, Rai-Min Huang
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Patent number: 11566629Abstract: A device for real-time self-diagnosis of a fan and a method are disclosed for detecting whether a fan body encounters an environment abnormal situation. The fan body includes a motor, a fan and a tachometer. The fan body further includes a microcontroller for receiving a speed signal of the tachometer and calculating a speed value of the fan, and detecting a current value of the motor during operation. The microcontroller can control the motor to drive the fan according to a monitoring period and a control signal transmitted from the control board, and can calculate a speed change amount according to the monitoring period, and can calculate a current change amount. When the speed change amount exceeds a speed change threshold and the current change amount exceeds a current change threshold for a period of time, the microcontroller generates an environmental anomaly signal.Type: GrantFiled: January 23, 2020Date of Patent: January 31, 2023Assignee: PROLIFIC TECHNOLOGY INC.Inventors: Chia Chang Hsu, Chih Feng Huang, Wei Shu Hsu
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Publication number: 20220392768Abstract: The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.Type: ApplicationFiled: June 7, 2021Publication date: December 8, 2022Applicant: United Microelectronics Corp.Inventors: Yi Jing Wang, Chia-Chang Hsu, Chien-Hao Chen, Chang-Mao Wang, Chun-Chi Yu
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Publication number: 20220376166Abstract: A semiconductor device includes a substrate, a first magnetic tunnel junction (MTJ) structure, a second MTJ structure, and an interconnection structure. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction, and the interconnection structure includes a first metal interconnection and a second metal interconnection. The second metal interconnection is disposed on and contacts the first metal interconnection. A material composition of the second metal interconnection is different from a material composition of the first metal interconnection.Type: ApplicationFiled: June 7, 2021Publication date: November 24, 2022Inventors: Chih-Wei Kuo, Chia-Chang Hsu