Patents by Inventor Chia-Chang Hsu

Chia-Chang Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200158761
    Abstract: Disclosures of the present invention describe a current sensing device and method, wherein the current sensing device comprises: at least one magnetic sensor, a signal receiving unit and a microprocessor. Particularly, the present invention provides an environmental magnetic field filtering unit and an effective current calculation unit in the microprocessor, such that the microprocessor is able to calculate the value of a current flowing in a specific electrical cable with high accuracy based on a sensing magnetic field outputted from the magnetic sensor.
    Type: Application
    Filed: November 26, 2018
    Publication date: May 21, 2020
    Inventor: Chia-Chang Hsu
  • Publication number: 20200136014
    Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a bottom electrode layer on the IMD layer, wherein the bottom electrode layer comprises a gradient concentration; forming a free layer on the bottom electrode layer; forming a top electrode layer on the free layer; and patterning the t op electrode layer, the free layer, and the bottom electrode layer to form a magnetic tunneling junction (MTJ).
    Type: Application
    Filed: November 26, 2018
    Publication date: April 30, 2020
    Inventors: Hui-Lin Wang, Chia-Chang Hsu, Chen-Yi Weng, Chin-Yang Hsieh, Jing-Yin Jhang
  • Patent number: 10503893
    Abstract: A security certificate management method for a vehicular network node is applied in a vehicular network. A message is received. Whether a certificate in the message is revoked is determined. If the certificate in the message is revoked, a regional certificate revocation list (RCRL) is generated or updated based on the revoked certificate by the vehicular network node, and the RCRL is transmitted into a communication range of the vehicular network node.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: December 10, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chia-Chang Hsu, Pei-Chuan Tsai, Huei-Ru Tseng, Jing-Shyang Hwu, Ping-Ta Tsai
  • Patent number: 10502790
    Abstract: The present invention discloses a battery internal resistance measuring device and a method thereof, wherein the battery internal resistance measuring device comprises a voltage detecting unit, at least one measurement resistor, at least one switch, and a measurement controller. By means of further explanation, the measurement controller at least comprises a differential value calculating unit for treating a differential value calculation or a slope calculation to each two of adjacent voltage sampling values on a waveform of a discharge voltage signal of the battery, such that the measurement controller can subsequently find out a discharge starting point and a discharge ending point according to data of the differential value calculations or the slope calculations. Eventually, the measurement controller calculates an internal resistance of the battery after picking up an open-circuit voltage and a short-circuit voltage from the discharge starting point and the discharge ending point.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: December 10, 2019
    Assignee: Prolific Technology Inc.
    Inventors: Yun-Kuo Lee, Chia-Chang Hsu, Ren-Yuan Yu, Ching-Te Chen
  • Publication number: 20190227615
    Abstract: The invention discloses a power saving device capable of automatically sensing standby current, which is used in a power device such as a power outlet or other power supply devices for giving the power device ability of electricity saving. When the power saving device normally works, a threshold current setting unit of a controlling and processing module is configured to automatically calculate a threshold current based on current signals sensed by a current detecting unit under different operation modes of at least one electrical device electrically connected to the power device. Moreover, when at least one standby current sensed from the electrical device is determined to be lower than the threshold current, the controlling and processing module immediately switches a switch unit to an open-circuit state, thereby causing the electrical device unable to receive electricity from the power device. Consequently, the power device exhibits the ability of power saving.
    Type: Application
    Filed: November 7, 2018
    Publication date: July 25, 2019
    Inventor: CHIA-CHANG HSU
  • Patent number: 10340350
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: July 2, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Min Chou, Yun-Tzu Chang, Wei-Ning Chen, Wei-Ming Hsiao, Chia-Chang Hsu, Kuo-Chih Lai, Yang-Ju Lu, Yen-Chen Chen, Chun-Yao Yang
  • Patent number: 10283412
    Abstract: A method for fabricating a semiconductor device is provided. A substrate having a dummy gate thereon is prepared. A spacer is disposed on a sidewall of the dummy gate. A source/drain region is disposed adjacent to the dummy gate. A sacrificial layer is then formed on the source/drain region. A cap layer is then formed on the sacrificial layer. A top surface of the cap layer is coplanar with a top surface of the dummy gate. A replacement metal gate (RMG) process is performed to transform the dummy gate into a replacement metal gate. An opening is then formed in the cap layer to expose a top surface of the sacrificial layer. The sacrificial layer is removed through the opening, thereby forming a lower contact hole exposing a top surface of the source/drain region. A lower contact plug is then formed in the lower contact hole.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: May 7, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia Chang Hsu, Chun-Hsien Lin
  • Publication number: 20180331193
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.
    Type: Application
    Filed: July 25, 2018
    Publication date: November 15, 2018
    Inventors: Shih-Min Chou, Yun-Tzu Chang, Wei-Ning Chen, Wei-Ming Hsiao, Chia-Chang Hsu, Kuo-Chih Lai, Yang-Ju Lu, Yen-Chen Chen, Chun-Yao Yang
  • Patent number: 10082543
    Abstract: In view of drivers cannot equip their vehicles with conventional intelligent battery monitoring system by themselves because the wire connections of the intelligent battery monitoring system are complex, the present invention particularly discloses a non-contact intelligent battery sensing system showing the advantages of simple circuit framework and low manufacturing cost. Since the non-contact intelligent battery sensing system only comprises a magnetic field sensor and a sensor controlling module, it is very easy for the drivers to equip their vehicles with this non-contact intelligent battery sensing system by themselves. To apply the non-contact intelligent battery sensing system, the driver just needs to firstly dispose the magnetic field sensor at one position near to a power line of a battery to be sensed, and then install a sensor controlling application program in his smart phones. Apparently, the non-contact intelligent battery sensing system further shows the advantage of easy to be installed.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: September 25, 2018
    Assignee: Prolific Technology Inc.
    Inventors: Yun-Kuo Lee, Chia-Chang Hsu, Ren-Yuan Yu, Ching-Te Chen, Ke-Ciang Shen
  • Publication number: 20180261675
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.
    Type: Application
    Filed: March 8, 2017
    Publication date: September 13, 2018
    Inventors: Shih-Min Chou, Yun-Tzu Chang, Wei-Ning Chen, Wei-Ming Hsiao, Chia-Chang Hsu, Kuo-Chih Lai, Yang-Ju Lu, Yen-Chen Chen, Chun-Yao Yang
  • Patent number: 10074725
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: September 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Min Chou, Yun-Tzu Chang, Wei-Ning Chen, Wei-Ming Hsiao, Chia-Chang Hsu, Kuo-Chih Lai, Yang-Ju Lu, Yen-Chen Chen, Chun-Yao Yang
  • Patent number: 10068797
    Abstract: A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: September 4, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Pin-Hong Chen, Kuo-Chih Lai, Chia Chang Hsu, Chun-Chieh Chiu, Li-Han Chen, Shu Min Huang, Min-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu
  • Publication number: 20180203075
    Abstract: The present invention discloses a battery internal resistance measuring device and a method thereof, wherein the battery internal resistance measuring device comprises a voltage detecting unit, at least one measurement resistor, at least one switch, and a measurement controller. By means of further explanation, the measurement controller at least comprises a differential value calculating unit for treating a differential value calculation or a slope calculation to each two of adjacent voltage sampling values on a waveform of a discharge voltage signal of the battery, such that the measurement controller can subsequently find out a discharge starting point and a discharge ending point according to data of the differential value calculations or the slope calculations. Eventually, the measurement controller calculates an internal resistance of the battery after picking up an open-circuit voltage and a short-circuit voltage from the discharge starting point and the discharge ending point.
    Type: Application
    Filed: December 20, 2017
    Publication date: July 19, 2018
    Inventors: YUN-KUO LEE, CHIA-CHANG HSU, REN-YUAN YU, CHING-TE CHEN
  • Publication number: 20180180679
    Abstract: In view of drivers cannot equip their vehicles with conventional intelligent battery monitoring system by themselves because the wire connections of the intelligent battery monitoring system are complex, the present invention particularly discloses a non-contact intelligent battery sensing system showing the advantages of simple circuit framework and low manufacturing cost. Since the non-contact intelligent battery sensing system only comprises a magnetic field sensor and a sensor controlling module, it is very easy for the drivers to equip their vehicles with this non-contact intelligent battery sensing system by themselves. To apply the non-contact intelligent battery sensing system, the driver just needs to firstly dispose the magnetic field sensor at one position near to a power line of a battery to be sensed, and then install a sensor controlling application program in his smart phones. Apparently, the non-contact intelligent battery sensing system further shows the advantage of easy to be installed.
    Type: Application
    Filed: April 27, 2017
    Publication date: June 28, 2018
    Inventors: YUN-KUO LEE, CHIA-CHANG HSU, REN-YUAN YU, CHING-TE CHEN, KE-CIANG SHEN
  • Patent number: 9985110
    Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: May 29, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Pin-Hong Chen, Kuo-Chih Lai, Chia-Chang Hsu, Chun-Chieh Chiu, Li-Han Chen, Min-Chuan Tsai, Kuo-Chin Hung, Wei-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu
  • Patent number: 9922974
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: March 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia Chang Hsu, Chun-Hsien Lin
  • Publication number: 20180012808
    Abstract: A method for fabricating a semiconductor device is provided. A substrate having a dummy gate thereon is prepared. A spacer is disposed on a sidewall of the dummy gate. A source/drain region is disposed adjacent to the dummy gate. A sacrificial layer is then formed on the source/drain region. A cap layer is then formed on the sacrificial layer. A top surface of the cap layer is coplanar with a top surface of the dummy gate. A replacement metal gate (RMG) process is performed to transform the dummy gate into a replacement metal gate. An opening is then formed in the cap layer to expose a top surface of the sacrificial layer. The sacrificial layer is removed through the opening, thereby forming a lower contact hole exposing a top surface of the source/drain region. A lower contact plug is then formed in the lower contact hole.
    Type: Application
    Filed: September 7, 2017
    Publication date: January 11, 2018
    Inventors: Chia Chang Hsu, Chun-Hsien Lin
  • Publication number: 20170323950
    Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.
    Type: Application
    Filed: July 21, 2017
    Publication date: November 9, 2017
    Applicant: United Microelectronics Corp.
    Inventors: Pin-Hong Chen, Kuo-Chih Lai, Chia-Chang Hsu, Chun-Chieh Chiu, Li-Han Chen, Min-Chuan Tsai, Kuo-Chin Hung, Wei-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu
  • Publication number: 20170301670
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate.
    Type: Application
    Filed: July 5, 2017
    Publication date: October 19, 2017
    Inventors: Chia Chang Hsu, Chun-Hsien Lin
  • Patent number: 9793170
    Abstract: A semiconductor device includes a substrate, a first gate structure on the substrate, a first spacer adjacent to the first gate structure, a lower contact plug adjacent to the first gate structure and contact the first spacer, and a first overhang feature disposed on an upper end of the first spacer.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: October 17, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia Chang Hsu, Chun-Hsien Lin