Abstract: The method includes forming a sacrificial multi-layer stack including alternating first sacrificial layers and second sacrificial layers stacked in a vertical direction on a substrate; removing the first sacrificial layers to form first spaces each interposing two of the second sacrificial layers; depositing a first dielectric layer and a first electrode material in the first spaces; removing the second sacrificial layers to form second spaces each interposing two portions of the first electrode material; depositing a second dielectric layer and a second electrode material in the second spaces.

Abstract: A method of forming a semiconductor device includes forming a semiconductor strip extending above a semiconductor substrate, forming shallow trench isolation (STI) regions on opposite sides of the semiconductor strip, recessing a portion of the semiconductor strip, etching the STI regions to form a recess in the STI regions, forming a first thermal conductive layer in the recess, forming a source/drain epitaxy structure on the first thermal conductive layer, and forming a gate stack across the semiconductor strip and extending over the STI regions.

Abstract: A device comprise a first semiconductor channel layer over a substrate, a second semiconductor channel layer over the first semiconductor channel layer, and source/drain epitaxial structures on opposite sides of the first semiconductor channel layer and opposite sides of the second semiconductor channel layer. A compressive strain in the second semiconductor channel layer is greater than a compressive strain in the first semiconductor channel layer. The source/drain epitaxial structures each comprise a first region interfacing the first semiconductor channel layer and a second region interfacing the second semiconductor channel layer, and the first region has a composition different from a composition of the second region.

Abstract: A device is provided. The device includes a memory cell and a first write assist circuit. The memory cell operates with a first supply voltage and a second supply voltage different from the first supply voltage. The first write assist circuit includes a first write assist switch and a second write assist switch that are coupled to the memory cell through a first data line. In a write operation of a data, having a first logic value, to the memory cell, the first write assist switch transmits the first supply voltage to the first data line in response to a first control signal, received at a control terminal of the first write assist switch and having a voltage level of the second supply voltage, when the second write assist switch is configured to be turned off.

Abstract: A device comprises a plurality of nanosheets, source/drain stressors, and a gate structure wrapping around the nanosheets. The nanosheets extend in a first direction above a semiconductor substrate and are arranged in a second direction substantially perpendicular to the first direction. The source/drain stressors are on either side of the nanosheets. Each of the source/drain stressors comprises a first epitaxial layer and a second epitaxial layer over the first epitaxial layer. The first and second epitaxial layers are made of a Group IV element and a Group V element. An atomic ratio of the Group V element to the Group IV element in the second epitaxial layer is greater than an atomic ratio of the Group V element to the Group IV element in the first epitaxial layer.

Abstract: A semiconductor device and method for forming same. According to an embodiment. The method provides a base substrate, forms a heat dissipation substrate on the base substrate, wherein a thermal conductivity of the heat dissipation substrate is between 200 Wm?1K?1and 1200 Wm?1K?1. This method further forms a device layer on the heat dissipation substrate, wherein the device layer comprises a transistor. The method further removes the base substrate.

Abstract: A semiconductor device includes a heat dissipation substrate and a device layer. The thermal conductivity of the heat dissipation substrate is greater than 200 Wm?1K?1 and the device layer is disposed on the heat dissipation substrate. The device layer includes a transistor. A method of forming a semiconductor device includes providing a base substrate, forming a heat dissipation substrate on the base substrate, wherein a thermal conductivity of the heat dissipation substrate is greater than 200 Wm?1K?1. The method further includes forming a device layer on the heat dissipation substrate, wherein the device layer comprises a transistor. The method further includes removing the base substrate.

Abstract: An IC structure comprises an MTJ cell, a transistor, a first word line, and a second word line. The transistor is electrically coupled to the MTJ cell. The transistor comprises a first gate terminal and a second gate terminal independent of the first gate terminal. The first word line is electrically coupled to the first gate terminal of the transistor. The second word line is electrically coupled to the second gate terminal of the transistor. A resistance state of the MTJ cell is dependent on a first word line voltage applied to the first word line and a second word line voltage applied to the second word line, and the resistance state of the MTJ cell follows an AND gate logic or an OR gate logic.

Abstract: A device is provided. The device includes a physical unclonable function (PUF) cell array. The PUF cell array includes multiple bit cells, and generates a PUF response output, in response to a challenge input, based on a data state of one bit cell in the bit cells. Each of the bit cells stores a bit data and includes a transistor having a control terminal coupled to a word line and a first terminal coupled to a source line, a first memory cell having a first terminal coupled to a first data line and a second terminal coupled to a second terminal of the transistor, and a second memory cell having a first terminal coupled to a second data line, different from the first data line, and a second terminal coupled to the second terminal of the first memory cell at the second terminal of the transistor.

Abstract: A device comprises a plurality of nanosheets, source/drain stressors, and a gate structure wrapping around the nanosheets. The nanosheets extend in a first direction above a semiconductor substrate and are arranged in a second direction substantially perpendicular to the first direction. The source/drain stressors are on either side of the nanosheets. Each of the source/drain stressors comprises a first epitaxial layer and a second epitaxial layer over the first epitaxial layer. The first and second epitaxial layers are made of a Group IV element and a Group V element. An atomic ratio of the Group V element to the Group IV element in the second epitaxial layer is greater than an atomic ratio of the Group V element to the Group IV element in the first epitaxial layer.

Abstract: A semiconductor device includes a heat dissipation substrate and a device layer. The thermal conductivity of the heat dissipation substrate is greater than 200 Wm?1K?1and the device layer is disposed on the heat dissipation substrate. The device layer includes a transistor.

Abstract: The present disclosure generally relates to a gate-all-around (GAA) transistor. The GAA transistor may include regrown source/drain layers in source/drain stressors. Atomic ratio differences among the regrown source/drain layers are tuned to reduce strain mismatch among the semiconductor nanosheets. Alternatively, the GAA transistor may include strained channels formed using a layer stack of alternating semiconductor layers having different lattice constants.

Abstract: A method includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate; forming a dummy gate structure across the fin structure; etching portions of the fin structure to expose portions of the substrate; forming source/drain stressors over the exposed portions of the substrate; after forming the source/drain stressors, removing the dummy gate structure; after removing the dummy gate structure, removing the first semiconductor layers such that the second semiconductor layers are suspended between the source/drain stressors; and forming a gate structure to surround each of the suspended second semiconductor layers. The source/drain stressors each comprise a first source/drain layer and a second source/drain layer over the first source/drain layer. An atomic concentration of a Group IV element or a Group V element in the second source/drain layer is greater than that in the first source/drain layer.

Abstract: A semiconductor device includes a substrate, a channel structure and a metal gate structure. The channel structure protrudes above the substrate. The channel structure includes alternately stacked first portions and second portions having widths greater than widths of the first portions, and the first portions and the second portions are made of the same semiconductor material. The metal gate structure wraps around the channel structure.

Abstract: A semiconductor device includes a substrate, a channel structure and a metal gate structure. The channel structure protrudes above the substrate. The channel structure includes alternately stacked first portions and second portions having widths greater than widths of the first portions, and the first portions and the second portions are made of the same semiconductor material. The metal gate structure wraps around the channel structure.

Abstract: A semiconductor device includes a substrate, a channel structure, and a gate structure. The channel structure is over the substrate and extends along a first direction, in which the channel structure has plurality of first portions and plurality of second portions alternately stacked, and a width of the first portions is smaller than that of the second portions in a second direction different from the first direction. The gate structure is disposed over the substrate and crossing the channel structure along the second direction, in which the gate structure is in contact with the first portions and the second portions.

Abstract: A semiconductor device includes a substrate, a channel structure, and a gate structure. The channel structure is over the substrate and extends along a first direction, in which the channel structure has plurality of first portions and plurality of second portions alternately stacked, and a width of the first portions is smaller than that of the second portions in a second direction different from the first direction. The gate structure is disposed over the substrate and crossing the channel structure along the second direction, in which the gate structure is in contact with the first portions and the second portions.

Abstract: An oxide polishing process that is part of a CMP process flow is disclosed. After a copper layer is polished at a first polishing station and a diffusion barrier layer is polished at a second polishing station, a key sequence at a third polish station is the application of a first oxide slurry and a first DI water rinse followed by a second oxide slurry and then a second DI water rinse. As a result, defect counts are reduced from several thousand to less than 100. Another important factor is a low down force that enables more efficient particle removal. The improved oxide polishing process has the same throughput as a single oxide polish and a DI water rinse method and may be implemented in any three slurry copper CMP process flow.