Patents by Inventor Chia-Che Chung

Chia-Che Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220149172
    Abstract: A device comprises a plurality of nanosheets, source/drain stressors, and a gate structure wrapping around the nanosheets. The nanosheets extend in a first direction above a semiconductor substrate and are arranged in a second direction substantially perpendicular to the first direction. The source/drain stressors are on either side of the nanosheets. Each of the source/drain stressors comprises a first epitaxial layer and a second epitaxial layer over the first epitaxial layer. The first and second epitaxial layers are made of a Group IV element and a Group V element. An atomic ratio of the Group V element to the Group IV element in the second epitaxial layer is greater than an atomic ratio of the Group V element to the Group IV element in the first epitaxial layer.
    Type: Application
    Filed: January 24, 2022
    Publication date: May 12, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chung-En TSAI, Chia-Che CHUNG, Chee-Wee LIU, Fang-Liang LU, Yu-Shiang HUANG, Hung-Yu YEH, Chien-Te TU, Yi-Chun LIU
  • Publication number: 20220059429
    Abstract: A semiconductor device includes a heat dissipation substrate and a device layer. The thermal conductivity of the heat dissipation substrate is greater than 200 Wm?1K?1and the device layer is disposed on the heat dissipation substrate. The device layer includes a transistor.
    Type: Application
    Filed: December 24, 2020
    Publication date: February 24, 2022
    Inventors: Ming-Tzong Yang, Hsien-Hsin Lin, Wen-Kai Wan, Chia-Che Chung, Chee-Wee Liu
  • Patent number: 11233120
    Abstract: The present disclosure generally relates to a gate-all-around (GAA) transistor. The GAA transistor may include regrown source/drain layers in source/drain stressors. Atomic ratio differences among the regrown source/drain layers are tuned to reduce strain mismatch among the semiconductor nanosheets. Alternatively, the GAA transistor may include strained channels formed using a layer stack of alternating semiconductor layers having different lattice constants.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: January 25, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chung-En Tsai, Chia-Che Chung, Chee-Wee Liu, Fang-Liang Lu, Yu-Shiang Huang, Hung-Yu Yeh, Chien-Te Tu, Yi-Chun Liu
  • Publication number: 20210328012
    Abstract: A method includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate; forming a dummy gate structure across the fin structure; etching portions of the fin structure to expose portions of the substrate; forming source/drain stressors over the exposed portions of the substrate; after forming the source/drain stressors, removing the dummy gate structure; after removing the dummy gate structure, removing the first semiconductor layers such that the second semiconductor layers are suspended between the source/drain stressors; and forming a gate structure to surround each of the suspended second semiconductor layers. The source/drain stressors each comprise a first source/drain layer and a second source/drain layer over the first source/drain layer. An atomic concentration of a Group IV element or a Group V element in the second source/drain layer is greater than that in the first source/drain layer.
    Type: Application
    Filed: April 16, 2020
    Publication date: October 21, 2021
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Chung-En TSAI, Chia-Che CHUNG, Chee-Wee LIU, Fang-Liang LU, Yu-Shiang HUANG, Hung-Yu YEH, Chien-Te TU, Yi-Chun LIU
  • Patent number: 11031470
    Abstract: A semiconductor device includes a substrate, a channel structure and a metal gate structure. The channel structure protrudes above the substrate. The channel structure includes alternately stacked first portions and second portions having widths greater than widths of the first portions, and the first portions and the second portions are made of the same semiconductor material. The metal gate structure wraps around the channel structure.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: June 8, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Fang-Liang Lu, Chia-Che Chung, Yu-Jiun Peng, Chee-Wee Liu
  • Publication number: 20200144368
    Abstract: A semiconductor device includes a substrate, a channel structure and a metal gate structure. The channel structure protrudes above the substrate. The channel structure includes alternately stacked first portions and second portions having widths greater than widths of the first portions, and the first portions and the second portions are made of the same semiconductor material. The metal gate structure wraps around the channel structure.
    Type: Application
    Filed: January 9, 2020
    Publication date: May 7, 2020
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Fang-Liang LU, Chia-Che CHUNG, Yu-Jiun PENG, Chee-Wee LIU
  • Patent number: 10535737
    Abstract: A semiconductor device includes a substrate, a channel structure, and a gate structure. The channel structure is over the substrate and extends along a first direction, in which the channel structure has plurality of first portions and plurality of second portions alternately stacked, and a width of the first portions is smaller than that of the second portions in a second direction different from the first direction. The gate structure is disposed over the substrate and crossing the channel structure along the second direction, in which the gate structure is in contact with the first portions and the second portions.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: January 14, 2020
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Fang-Liang Lu, Chia-Che Chung, Yu-Jiun Peng, Chee-Wee Liu
  • Publication number: 20190131403
    Abstract: A semiconductor device includes a substrate, a channel structure, and a gate structure. The channel structure is over the substrate and extends along a first direction, in which the channel structure has plurality of first portions and plurality of second portions alternately stacked, and a width of the first portions is smaller than that of the second portions in a second direction different from the first direction. The gate structure is disposed over the substrate and crossing the channel structure along the second direction, in which the gate structure is in contact with the first portions and the second portions.
    Type: Application
    Filed: October 27, 2017
    Publication date: May 2, 2019
    Inventors: Fang-Liang LU, Chia-Che CHUNG, Yu-Jiun PENG, Chee-Wee LIU
  • Patent number: 6946397
    Abstract: An oxide polishing process that is part of a CMP process flow is disclosed. After a copper layer is polished at a first polishing station and a diffusion barrier layer is polished at a second polishing station, a key sequence at a third polish station is the application of a first oxide slurry and a first DI water rinse followed by a second oxide slurry and then a second DI water rinse. As a result, defect counts are reduced from several thousand to less than 100. Another important factor is a low down force that enables more efficient particle removal. The improved oxide polishing process has the same throughput as a single oxide polish and a DI water rinse method and may be implemented in any three slurry copper CMP process flow.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: September 20, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: William Hong, Chia-Che Chung, Chi-Wei Chung, Wen-Chih Chiou, Ying-Ho Chen, Syun-Ming Jang