Abstract: The present invention relates to a method for preparing a modified stem cell, including the following steps: a cell culture step: culturing stem cells in a first culture medium of a culture dish at a predetermined cell density, and removing the first culture medium after a first culture time to obtain a first cell intermediate; an activity stimulation step: preserving the first cell intermediate in a freezing container having a cell cryopreservation solution, and performing a constant temperature stimulation treatment or a variable temperature stimulation treatment for at least more than 1 day; and a product collection step: after completing the activity stimulation step, placing the freezing container in an environment at a thawing temperature for thawing, and then removing the cell cryopreservation solution to obtain the modified stem cell. The modified stem cell can release at least one or more of IL-4, IL-5, IL-13, G-CSF, Fractalkine, and EGF.

Abstract: A manufacturing method for a LED is disclosed. The method includes: providing a substrate with an upper surface; preparing a plurality of LEDs on the upper surface; wherein the upper surface is divided into a plurality of zones, the plurality of LEDs composes a plurality of LED groups, and each of the LED group is disposed in one of the plurality of zones; preparing a testing circuit to electrically connecting the plurality of LEDs in one of the plurality of LED groups; testing the plurality of LEDs in the one of the plurality of LED groups by the testing circuit to obtain photoelectrical characteristics of the plurality of LEDs in the one of the plurality of LED groups; and presenting the photoelectric characteristics in an image.

Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.

Abstract: A button mechanism includes a button, a module, and a thin sheet spring. The thin sheet spring is in physical communication with the button and with the module. The thin sheet spring exerts a tension force on the button and the module to bias the button toward a normal position. In response to a force greater than the tension force being exerted on the button, a portion of the thin sheet stretches to enable the button to be placed in a contact position. In response to the force being removed from the button, the tension force causes the thin sheet to snap back to an original position and biases the button toward the normal position.

Abstract: A manufacturing method for an LED includes: providing a substrate having an upper surface divided into a plurality of zones; a LED group formed on each of the zones and wherein: a plurality of the LED groups includes a first LED group; and the LEDs of the first LED group include a defective LED; forming a testing circuit on the substrate to electrically connect the LEDs; testing the first LED group by the testing circuit; recording a position of the defective LED; providing a carrier; and performing one of the following steps by the position of the defective LED: removing the defective LED from the substrate and then transferring the other LEDs in the first LED group to the carrier; transferring the other LEDs other than the defective LED in the first LED group to the carrier; or transferring the LEDs to the carrier and repairing it on the carrier.

Abstract: An NMOS structure includes a semiconductor substrate, a dielectric structure, a source doped region, a drain doped region, a channel region, a gate structure and two isolation P-type wells. The dielectric structure is formed in the semiconductor substrate to define an active region, in which the source/drain doped region and the channel region are formed. The channel region includes two opposite first sides and two opposite second sides. The source/drain doped region is respectively formed between the two second sides and the dielectric structure. The gate structure is formed on the semiconductor substrate. The gate structure covers a part of the dielectric structure beside the first sides. The two isolation P-type wells are formed in a part of the dielectric structure not covered by the gate structure. The isolation P-type wells respectively surround a periphery of the source/drain doped region and end at the respective second side.

Abstract: A manufacturing method for an LED includes: providing a substrate having an upper surface divided into a plurality of zones; a LED group formed on each of the zones and wherein: a plurality of the LED groups includes a first LED group; and the LEDs of the first LED group include a defective LED; forming a testing circuit on the substrate to electrically connect the LEDs; testing the first LED group by the testing circuit; recording a position of the defective LED; providing a carrier; and performing one of the following steps by the position of the defective LED: removing the defective LED from the substrate and then transferring the other LEDs in the first LED group to the carrier; transferring the other LEDs other than the defective LED in the first LED group to the carrier; or transferring the LEDs to the carrier and repairing it on the carrier.

Abstract: A light-emitting device includes a first semiconductor layer having an uppermost surface and a bottommost surface; a first light-emitting structure and a second light-emitting structure formed on the same first semiconductor layer, wherein the first semiconductor layer is continuous; a first trench formed between the first and the second light-emitting structures; and a second electrode formed on the second semiconductor layer and including a second pad and a plurality of second extending parts extending from the second pad; wherein the second pad is between the first and the second light-emitting structures, and the plurality of second extending parts extends to the first and the second light-emitting structures, respectively; wherein the first trench passes through the uppermost surface but does not extend to the bottommost surface; wherein the first trench includes an equal width in a top view.

Abstract: A manufacturing method of a semiconductor device includes following steps. First gate structures and second gate structures are formed on a first region and a second region of a semiconductor substrate respectively. A spacing distance between the second gate structures is larger than that between the first gate structures. A first ion implantation is preformed to form a first doped region between the first gate structures. A second ion implantation is performed to form a second doped region between the second gate structures. A tilt angle of the second ion implantation is larger than that of the first ion implantation. An implantation dose of the second ion implantation is lower than that of the first ion implantation. An etching process is performed to at least partially remove the first doped region to form a first recess and at least partially remove the second doped region to form a second recess.

Abstract: A compound semiconductor device includes a substrate, including a top surface, a bottom surface, a side surface connecting the top surface and the bottom surface; and a semiconductor stack formed on the top surface, wherein the side surface includes a first deteriorated surface, a second deteriorated surface, a first crack surface between the first and second deteriorated surfaces, a second crack surface between the first deteriorated surface and the top surface, and a third crack surface between the second deteriorated surface and the bottom surface, wherein the first crack surface is inclined to the first deteriorated surface or the second deteriorated surface; and wherein the second crack surface or the third crack surface is substantially perpendicular to the top surface or the bottom surface.

Abstract: A light-emitting device includes a first semiconductor layer having an uppermost surface and a bottommost surface; a first light-emitting structure and a second light-emitting structure formed on the same first semiconductor layer, wherein the first semiconductor layer is continuous; a first trench formed between the first and the second light-emitting structures; and a second electrode formed on the second semiconductor layer and including a second pad and a plurality of second extending parts extending from the second pad; wherein the second pad is between the first and the second light-emitting structures, and the plurality of second extending parts extends to the first and the second light-emitting structures, respectively; wherein the first trench passes through the uppermost surface but does not extend to the bottommost surface; wherein the first trench includes an equal width in a top view.

Abstract: A light-emitting device includes a first semiconductor layer; a first, a second and a third light-emitting structures formed on the same first semiconductor layer; a first trench between the first and the second light-emitting structures; a second trench between the second and the third light-emitting structures, wherein the first and the second trenches include bottom portions exposing a surface of the first semiconductor layer; a third trench in one of the light-emitting structures, exposing the first semiconductor layer and extending along a direction parallel with the first semiconductor layer; an insulating bridge part in the first and the second trenches, connecting the light-emitting structures; a first electrode in the third trench, electrically connecting to the first semiconductor layer; and a second electrode, including a pad on one of the light-emitting structures and an extending part; wherein the extending part is formed on the insulating bridge part and extends to the light-emitting structures.

Abstract: A manufacturing method of a semiconductor device includes following steps. First gate structures and second gate structures are formed on a first region and a second region of a semiconductor substrate respectively. A spacing distance between the second gate structures is larger than that between the first gate structures. A first ion implantation is preformed to form a first doped region between the first gate structures. A second ion implantation is performed to form a second doped region between the second gate structures. A tilt angle of the second ion implantation is larger than that of the first ion implantation. An implantation dose of the second ion implantation is lower than that of the first ion implantation. An etching process is performed to at least partially remove the first doped region to form a first recess and at least partially remove the second doped region to form a second recess.

Abstract: A compound semiconductor device includes a substrate, including a top surface, a bottom surface, a side surface connecting the top surface and the bottom surface; and a semiconductor stack formed on the top surface, wherein the side surface includes a first deteriorated surface, a second deteriorated surface, a first crack surface between the first and second deteriorated surfaces, a second crack surface between the first deteriorated surface and the top surface, and a third crack surface between the second deteriorated surface and the bottom surface, wherein the first crack surface is inclined to the first deteriorated surface or the second deteriorated surface; and wherein the second crack surface or the third crack surface is substantially perpendicular to the top surface or the bottom surface.

Abstract: A compound semiconductor device includes a substrate, including a top surface, a bottom surface, a side surface connecting the top surface and the bottom surface; and a semiconductor stack formed on the top surface, wherein the side surface includes a first deteriorated surface, a second deteriorated surface, a first crack surface between the first and second deteriorated surfaces, a second crack surface between the first deteriorated surface and the top surface, and a third crack surface between the second deteriorated surface and the bottom surface, wherein a convex region or a concave region is formed by the first deteriorated surface, the first crack surface and the second crack surface, or the second deteriorated surface, the first crack surface and the third crack surface; and wherein the second crack surface or the third crack surface is substantially perpendicular to the top surface or the bottom surface.

Abstract: A compound semiconductor device includes a substrate, including a top surface, a bottom surface, a side surface connecting the top surface and the bottom surface; and a semiconductor stack formed on the top surface, wherein the side surface includes a first deteriorated surface, a second deteriorated surface, a first crack surface between the first and second deteriorated surfaces, a second crack surface between the first deteriorated surface and the top surface, and a third crack surface between the second deteriorated surface and the bottom surface, wherein a convex region or a concave region is formed by the first deteriorated surface, the first crack surface and the second crack surface, or the second deteriorated surface, the first crack surface and the third crack surface; and wherein the second crack surface or the third crack surface is substantially perpendicular to the top surface or the bottom surface.

Abstract: A compound semiconductor device comprises a substrate, comprising a top surface, a bottom surface, a side surface connecting the top surface and the bottom surface; and a semiconductor stack formed on the top surface, wherein the side surface comprises a first deteriorated surface, a second deteriorated surface, a first crack surface between the first and second deteriorated surfaces, a second crack surface between the first deteriorated surface and the top surface, and a third crack surface between the second deteriorated surface and the bottom surface, wherein the first and second deteriorated surfaces are rougher than at least one of the first crack surface, the second crack surface and the third crack surface; and wherein the second crack surface is about perpendicular to the top surface, and the third crack surface is about perpendicular to the bottom surface.

Abstract: A light-emitting element, includes a substrate; a light-emitting stack formed on the substrate, including a triangular upper surface parallel to the substrate, having three sides and three vertexes; a first electrode formed on the light-emitting stack and located near a first vertex of the three vertexes of the triangular upper surface; and a second electrode formed on the light-emitting stack; including two second electrode pads respectively located near other two vertexes of the three vertexes; and a second electrode extending part extending from the second electrode pads, disposed along the three sides of the triangular upper surface.

Abstract: A light-emitting device includes a first semiconductor layer; a first, a second and a third light-emitting structures formed on the same first semiconductor layer; a first trench between the first and the second light-emitting structures; a second trench between the second and the third light-emitting structures, wherein the first and the second trenches include bottom portions exposing a surface of the first semiconductor layer; a third trench in one of the light-emitting structures, exposing the first semiconductor layer and extending along a direction parallel with the first semiconductor layer; an insulating bridge part in the first and the second trenches, connecting the light-emitting structures; a first electrode in the third trench, electrically connecting to the first semiconductor layer; and a second electrode, including a pad on one of the light-emitting structures and an extending part; wherein the extending part is formed on the insulating bridge part and extends to the light-emitting structures.

Abstract: A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.