Patents by Inventor Chia-Cheng Chen

Chia-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10459492
    Abstract: An electronic device includes a first machine body, a second machine body, a hinge structure, a moving component, and a towing structure. The hinge structure is configured to pivot the first machine body and the second machine body. The moving component is movably disposed in the first machine body. The towing structure is disposed in the first machine body and is coupled to the hinge structure and the moving component. The towing structure is configured to be driven by the hinge structure to drive the moving component to move relative to the first machine body.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 29, 2019
    Assignee: Wistron Corporation
    Inventors: Jing-Lung Chen, Chia-Lung Hsu, Yao-Jheng Chen, Po-Cheng Chen
  • Patent number: 10462928
    Abstract: A composite cable assembly includes flat cables, a cable unit and fastening units. Each flat cable includes conductor assemblies and a shielding layer covering the conductor assemblies. The cable unit includes transmission lines. The transmission lines are arranged horizontally and in contact with the shielding layer of the flat cable closest to the transmission lines. The cable unit contacts the flat cable closest to the cable unit, the cable unit and each flat cable are together bent to form bent portions and extension sections connected to the bent portions. Each two fastening units are arranged spaced apart at two sides of a corresponding bent portion. Each extension section has the same length when the cable unit and each flat cable are moved in a movement direction to extend or collapse.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: October 29, 2019
    Assignee: SUPER MICRO COMPUTER INC.
    Inventors: Hsiao-Chung Chen, Tan-Hsin Chang, Chia-Cheng Lu, Chih-Wei Chen
  • Publication number: 20190322762
    Abstract: An antibody, or an antigen-binding fragment there, binding human ENO1 (GenBank: AAH506421.1) is provided. Methods for treating an ENO1 protein-related disease or disorder, inhibiting cancer invasion and diagnosis of cancer are also provided.
    Type: Application
    Filed: March 19, 2018
    Publication date: October 24, 2019
    Applicants: DEVELOPMENT CENTER FOR BIOTECHNOLOGY, NATIONAL HEALTH RESEARCH INSTITUTES
    Inventors: SHIH-CHONG TSAI, TA-TUNG YUAN, SHIH-CHI TSENG, JIANN-SHIUN LAI, CHIA-CHENG WU, PO-YIN LIN, YA-WEI TSAI, CHAO-YANG HUANG, YING-YUNG LOK, CHUNG-HSIUN WU, HSIEN-YU TSAI, NENG-YAO SHIH, KO-JIUNN LIU, LI-TZONG CHEN
  • Publication number: 20190320370
    Abstract: A multi-member Bluetooth device includes: a main Bluetooth circuit capable of directly communicating with a remote Bluetooth device through a Bluetooth transmission approach; and an auxiliary Bluetooth circuit capable of indirectly communicating with the remote Bluetooth device through the main Bluetooth circuit. After operating for a certain period, the main Bluetooth circuit transmits the main Bluetooth circuit's device identification data and multiple Bluetooth connection parameters between the main Bluetooth circuit and the remote Bluetooth device to the auxiliary Bluetooth circuit.
    Type: Application
    Filed: April 11, 2019
    Publication date: October 17, 2019
    Applicant: Realtek Semiconductor Corp.
    Inventors: Yi-Cheng CHEN, Kuan-Chung HUANG, Chia-Chun HUNG
  • Publication number: 20190320478
    Abstract: A multi-member Bluetooth network includes: a main Bluetooth circuit capable of directly communicating with a remote Bluetooth device through a Bluetooth transmission approach; and an auxiliary Bluetooth circuit capable of indirectly communicating with the remote Bluetooth device through the main Bluetooth circuit. When the auxiliary Bluetooth circuit becomes more closer to the remote Bluetooth device than the main Bluetooth circuit, the main Bluetooth circuit instructs the auxiliary Bluetooth circuit to utilize the device identification data and multiple Bluetooth connection parameters of the main Bluetooth circuit to directly communicate with the remote Bluetooth device through a Bluetooth transmission approach by imitating the main Bluetooth circuit, and the main Bluetooth circuit then indirectly communicates with the remote Bluetooth device through the auxiliary Bluetooth circuit.
    Type: Application
    Filed: April 11, 2019
    Publication date: October 17, 2019
    Applicant: Realtek Semiconductor Corp.
    Inventors: Yi-Cheng CHEN, Kuan-Chung HUANG, Chia-Chun HUNG
  • Publication number: 20190309092
    Abstract: The present invention provides a modified antigen-binding Fab fragment. An antigen-binding molecule comprising the antigen-binding Fab fragment and a composition comprising the molecule are also provided.
    Type: Application
    Filed: July 20, 2017
    Publication date: October 10, 2019
    Applicant: Development Center for Biotechnology
    Inventors: Chih-Yung HU, Chao-Yang HUANG, Yu-Jung CHEN, Chia-Cheng WU, Chien-Tsun KUAN, Chia-Hsiang LO, Hsien-Yu TSAI
  • Publication number: 20190304864
    Abstract: A package structure including a semiconductor die, an insulating encapsulant, and a redistribution layer is provided. The semiconductor die includes a semiconductor substrate, a plurality of metallization layers disposed on the semiconductor substrate, and a passivation layer disposed on the plurality of metallization layers. The passivation layer has a first opening that partially expose a topmost layer of the plurality of metallization layers. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer includes at least a first dielectric layer and a first conductive layer stacked on the first dielectric layer. The first dielectric layer has a second opening that overlaps with the first opening, and a width ratio of the second opening to the first opening is in a range of 2.3:1 to 12:1. The first conductive layer is electrically connected to the topmost layer of the plurality of metallization layers through the first and second openings.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Ting Kuo, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Chih-Hsuan Tai, Ying-Cheng Tseng
  • Patent number: 10431535
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming an antenna structure in contact with one side of a circuit structure of a packaging substrate, and disposing an electronic component on the other side of the circuit structure. As such, the antenna structure is integrated with the packaging substrate, thereby reducing the thickness of the electronic package and improving the efficiency of the antenna structure.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: October 1, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Jui-Feng Chen, Chia-Cheng Hsu, Wen-Jung Tsai, Chia-Cheng Chen, Cheng Kai Chang
  • Publication number: 20190292586
    Abstract: Disclosed herein is a method of quantifying a mutant allele burden of a target gene in a subject. The method includes providing a first plasmid that includes a mutant allele sequence and an internal control sequence, and a second plasmid that includes a wild-type allele sequence and the internal control sequence, and subjecting DNA of the subject to quantitative polymerase chain reaction to measure a mutant allele expression level of the target gene, so as to determine the mutant allele burden of the target gene in the subject based on a standard curve of the mutant allele burden of the target gene created by serial dilution of the first and second plasmids.
    Type: Application
    Filed: March 19, 2019
    Publication date: September 26, 2019
    Inventors: Chih-Cheng CHEN, Chia-Chen HSU
  • Publication number: 20190288068
    Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.
    Type: Application
    Filed: June 6, 2019
    Publication date: September 19, 2019
    Inventors: Su-Hao Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Kuo-Ju Chen, Chun-Hung Wu, Chang-Maio Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
  • Publication number: 20190287190
    Abstract: A method of battery charging is to be implemented by an energy station communicable with a cloud server that stores reference battery identifiers. The method includes: detecting a provided battery identifier of a battery, and transmitting the provided battery identifier to the cloud server so as to enable the cloud server to determine one of the reference battery identifiers that matches the provided battery identifier, and to determine to which one of first and second lease codes the one of the reference battery identifiers thus determined corresponds; and being controlled to charge the battery when it is determined that the one of the reference battery identifiers thus determined by the cloud server corresponds to the first lease code.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 19, 2019
    Inventors: Chia-Cheng TU, Chi-Wei TIEN, Chien-Hung CHEN
  • Patent number: 10418460
    Abstract: A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation region that separates a first and second active region. The first active region is adjacent to a first side of the isolation region and the second active region is adjacent to a second side of the isolation region. A device including a source, a drain, and a gate is formed within the first active region. One of the source and drain regions are disposed adjacent to the isolation region. A dummy gate is formed at least partially over the isolation region and adjacent to the one of the source and drain regions. In various examples, the gate includes a first dielectric layer having a first thickness and the dummy gate includes a second dielectric layer having a second thickness greater than the first thickness.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: September 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chu Liu, Kuei-Shun Chen, Chiang Mu-Chi, Chao-Cheng Chen
  • Publication number: 20190280502
    Abstract: A charger management method to be implemented by a server includes steps of: with respect to each charger, in response to receipt from the charger in a non-charging state of a notification including a charger identifier (ID) of the charger, updating the state flag of one of charger information sets stored in the server and including the charger ID to a second value; and in response to receipt of a query including a target location from a user end electronic device, selecting, based on the charger information sets and the target location, at least one candidate charging station information set from multiple charging station information sets.
    Type: Application
    Filed: February 25, 2019
    Publication date: September 12, 2019
    Inventors: Ping-Jui HSIEH, Chia-Cheng TU, Te-Chuan LIU, Jen-Chiun LIN, Yuh-Rey CHEN, Po-Yu CHUANG
  • Patent number: 10395937
    Abstract: A method of forming a semiconductor device is disclosed. The method includes providing a device having a substrate and a hard mask layer over the substrate; forming a mandrel over the hard mask layer; depositing a material layer on sidewalls of the mandrel; implanting a dopant into the material layer; performing an etching process on the hard mask layer using the mandrel and the material layer as an etching mask, thereby forming a patterned hard mask layer, wherein the etching process concurrently produces a dielectric layer deposited on sidewalls of the patterned hard mask layer, the dielectric layer containing the dopant; and forming a fin by etching the substrate using the patterned hard mask layer and the dielectric layer collectively as an etching mask.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: August 27, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Tzung-Yi Tsai, Yen-Ming Chen, Dian-Hau Chen, Han-Ting Tsai, Tsung-Lin Lee, Chia-Cheng Ho, Ming-Shiang Lin
  • Publication number: 20190258770
    Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.
    Type: Application
    Filed: May 6, 2019
    Publication date: August 22, 2019
    Inventors: Yun-Lin Wu, Cheng-Cheng Kuo, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen, Yuan-Hsiang Lung, Yan-Tso Tsai
  • Publication number: 20190258156
    Abstract: A photomask includes a pattern region and a plurality of defects in the pattern region. The photomask further includes a first fiducial mark outside of the pattern region, wherein the first fiducial mark includes identifying information for the photomask, the first fiducial mark has a first size and a first shape. The photomask further includes a second fiducial mark outside of the pattern region. The second fiducial mark has a second size different from the first size, or a second shape different from the first shape.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Inventors: Hsin-Chang LEE, Chia-Jen CHEN, Chih-Cheng LIN, Ping-Hsun LIN
  • Publication number: 20190247522
    Abstract: A biocompatible magnetic material containing an iron oxide nanoparticle and one or more biocompatible polymers, each having formula (I) below, covalently bonded to the iron oxide nanoparticle: in which each of variables R, L, x, and y is defined herein, the biocompatible magnetic material contains 4-15% Fe(II) ions relative to the total iron ions. Also disclosed in a method of preparing the biocompatible magnetic material.
    Type: Application
    Filed: November 29, 2018
    Publication date: August 15, 2019
    Inventors: Wen-Yuan Hsieh, Yuan-Hung Hsu, Chia-Wen Huang, Ming-Cheng Wei, Chih-Lung Chen, Shian-Jy Wang
  • Publication number: 20190244907
    Abstract: A semiconductor package structure includes a first conductive structure, a second conductive structure, a first semiconductor component, a second semiconductor component and a first encapsulant. The first semiconductor component is disposed on the first conductive structure. The first conductive structure includes a first redistribution layer. The second semiconductor component is disposed on the second conductive structure. The second conductive structure includes a second redistribution layer, and the first conductive structure is electrically connected to the second conductive structure. The first encapsulant covers the first semiconductor component and the first conductive structure. A lateral surface of the first conductive structure and a lateral surface of the first encapsulant are non-coplanar.
    Type: Application
    Filed: February 5, 2018
    Publication date: August 8, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Guo-Cheng LIAO, Chia Ching CHEN, Yi Chuan DING
  • Publication number: 20190245057
    Abstract: An embodiment fin field-effect-transistor (finFET) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of the channel region. The gate oxide includes a thinnest portion having a first thickness and a thickest portion having a second thickness different than the first thickness. A difference between the first thickness and the second thickness is less than a maximum thickness variation, and the maximum thickness variation is in accordance with an operating voltage of the finFET.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 8, 2019
    Inventors: Chia-Cheng Chen, Meng-Shu Lin, Liang-Yin Chen, Xiong-Fei Yu, Syun-Ming Jang, Hui-Cheng Chang
  • Publication number: 20190236326
    Abstract: A fingerprint sensor includes a die, a plurality of conductive structures, an encapsulant, a plurality of conductive patterns, a first dielectric layer, a second dielectric layer, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The conductive patterns are over the die and are electrically connected to the die and the conductive structures. Top surfaces of the conductive patterns are flat. The first dielectric layer is over the die and the encapsulant. A top surface of the first dielectric layer is coplanar with top surfaces of the conductive patterns. The second dielectric layer covers the first dielectric layer and the conductive patterns. The redistribution structure is over the rear surface of the die.
    Type: Application
    Filed: January 30, 2018
    Publication date: August 1, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ying-Cheng Tseng