Patents by Inventor Chia-Cheng Chen

Chia-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10164066
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes forming a capping layer over a fin of a fin field effect transistor (finFET), where the fin is formed of a material comprising germanium. The method also includes forming a dummy dielectric layer over the capping layer. The method also includes forming a dummy gate over the dummy dielectric layer. The method also includes removing the dummy gate.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chen, Huicheng Chang, Liang-Yin Chen
  • Patent number: 10141266
    Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: November 27, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Cheng Pai, Wei-Chung Hsiao, Shih-Chao Chiu, Chun-Hsien Lin, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Patent number: 10128368
    Abstract: A double gate trench power transistor and manufacturing method thereof are provided. The double gate trench power transistor gate structure includes an epitaxial layer, a trench structure formed in the epitaxial layer, at least two gate structures, and a shielding electrode structure. The trench structure includes a deep trench portion and two shallow trench portions respectively adjacent to two opposite sides of the deep trench portion. Each of the gate structures formed in each of the shallow trench portions includes a gate insulating layer and a gate electrode. The gate insulating layer has a first dielectric layer, a second dielectric layer and a third dielectric layer. The second dielectric layer is interposed between the first and third dielectric layers. Additionally, a portion of the gate insulating layer is in contact with a shielding dielectric layer of the shielding electrode structure.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: November 13, 2018
    Assignee: SINOPOWER SEMICONDUCTOR, INC.
    Inventors: Po-Hsien Li, Jia-Fu Lin, Chia-Cheng Chen, Wei-Chieh Lin
  • Publication number: 20180316083
    Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming an antenna structure in contact with one side of a circuit structure of a packaging substrate, and disposing an electronic component on the other side of the circuit structure. As such, the antenna structure is integrated with the packaging substrate, thereby reducing the thickness of the electronic package and improving the efficiency of the antenna structure.
    Type: Application
    Filed: August 18, 2017
    Publication date: November 1, 2018
    Inventors: Jui-Feng Chen, Chia-Cheng Hsu, Wen-Jung Tsai, Chia-Cheng Chen, Cheng Kai Chang
  • Patent number: 10068842
    Abstract: A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: September 4, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shih-Chao Chiu, Chun-Hsien Lin, Yu-Cheng Pai, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Patent number: 10043757
    Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.
    Type: Grant
    Filed: May 10, 2015
    Date of Patent: August 7, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Cheng Pai, Wei-Chung Hsiao, Shih-Chao Chiu, Chun-Hsien Lin, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Patent number: 10002825
    Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: June 19, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shih-Chao Chiu, Chun-Hsien Lin, Yu-Cheng Pai, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Patent number: 9991197
    Abstract: A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: June 5, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chia-Cheng Chen, Chi-Ching Ho, Shao-Tzu Tang, Yu-Che Liu, Ying-Chou Tsai
  • Publication number: 20180151701
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes forming a first gate spacer is formed over a dummy gate of a fin field effect transistor (finFET). The method also includes performing a carbon plasma doping of the first gate spacer. The method also includes forming a plurality of source/drain regions, where a source/drain region is disposed on opposite sides of the dummy gate. The method also includes removing dummy gate.
    Type: Application
    Filed: March 29, 2017
    Publication date: May 31, 2018
    Inventors: Chia-Cheng Chen, Huicheng Chang, Liang-Yin Chen, Chun-Feng Nieh, Li-Ting Wang, Wan-Yi Kao, Chia-Ling Chan
  • Publication number: 20180151704
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes forming a capping layer over a fin of a fin field effect transistor (finFET), where the fin is formed of a material comprising germanium. The method also includes forming a dummy dielectric layer over the capping layer. The method also includes forming a dummy gate over the dummy dielectric layer. The method also includes removing the dummy gate.
    Type: Application
    Filed: July 3, 2017
    Publication date: May 31, 2018
    Inventors: CHIA-CHENG CHEN, HUICHENG CHANG, LIANG-YIN CHEN
  • Publication number: 20180145143
    Abstract: An embodiment fin field-effect-transistor (finFET) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of the channel region. The gate oxide includes a thinnest portion having a first thickness and a thickest portion having a second thickness different than the first thickness. A difference between the first thickness and the second thickness is less than a maximum thickness variation, and the maximum thickness variation is in accordance with an operating voltage of the finFET.
    Type: Application
    Filed: November 21, 2016
    Publication date: May 24, 2018
    Inventors: Chia-Cheng Chen, Liang-Yin Chen, Xiong-Fei Yu, Syun-Ming Jang, Hui-Cheng Chang, Meng-Shu Lin
  • Patent number: 9922827
    Abstract: A method of cleaning a semiconductor structure includes rotating a semiconductor structure. The method of cleaning further includes cleaning the semiconductor structure with a hydrogen fluoride (HF)-containing gas. A method of forming a semiconductor device includes forming a recess in a source/drain (S/D) region of a transistor. The method of forming further includes cleaning the recess with a HF-containing gas, the HF-containing gas having an oxide removing rate of about 2 nanometer/minute (nm/min) or less. The method of forming further includes epitaxially forming a strain structure in the recess after the cleaning the recess, the strain structure providing a strain to a channel region of the transistor.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: March 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Liang-Gi Yao, Chia-Cheng Chen, Ta-Ming Kuan, Jeff J. Xu, Clement Hsingjen Wann
  • Patent number: 9899249
    Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: February 20, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Cheng Pai, Chun-Hsien Lin, Shih-Chao Chiu, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Patent number: 9893160
    Abstract: A method of fabricating a semiconductor device includes contacting water with a silicon oxide layer. The method further includes diffusing an ozone-containing gas through water to treat the silicon oxide layer. The method further includes forming a dielectric layer over the treated silicon oxide layer.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: February 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Liang-Gi Yao, Chia-Cheng Chen, Clement Hsingjen Wann
  • Publication number: 20170352615
    Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.
    Type: Application
    Filed: June 16, 2017
    Publication date: December 7, 2017
    Inventors: Shih-Chao Chiu, Chun-Hsien Lin, Yu-Cheng Pai, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Publication number: 20170309537
    Abstract: A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.
    Type: Application
    Filed: July 12, 2017
    Publication date: October 26, 2017
    Inventors: Shih-Chao Chiu, Chun-Hsien Lin, Yu-Cheng Pai, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Publication number: 20170301658
    Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a dielectric layer on the carrier; forming a plurality of conductive posts in the dielectric layer; and forming a cavity in the dielectric layer to expose the bonding pads, wherein the conductive posts are positioned around a periphery of the cavity, thereby simplifying the fabrication process.
    Type: Application
    Filed: June 28, 2017
    Publication date: October 19, 2017
    Inventors: Yu-Cheng Pai, Chun-Hsien Lin, Shih-Chao Chiu, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Publication number: 20170294372
    Abstract: A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods.
    Type: Application
    Filed: June 26, 2017
    Publication date: October 12, 2017
    Inventors: Chia-Cheng Chen, Chi-Ching Ho, Shao-Tzu Tang, Yu-Che Liu, Ying-Chou Tsai
  • Publication number: 20170287840
    Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.
    Type: Application
    Filed: June 13, 2017
    Publication date: October 5, 2017
    Inventors: Yu-Cheng Pai, Wei-Chung Hsiao, Shih-Chao Chiu, Chun-Hsien Lin, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Patent number: 9735080
    Abstract: A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: August 15, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shih-Chao Chiu, Chun-Hsien Lin, Yu-Cheng Pai, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen