Patents by Inventor Chia-Cheng Chen

Chia-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9716060
    Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: July 25, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Shih-Chao Chiu, Chun-Hsien Lin, Yu-Cheng Pai, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Publication number: 20170200822
    Abstract: A double gate trench power transistor and manufacturing method thereof are provided. The double gate trench power transistor gate structure includes an epitaxial layer, a trench structure formed in the epitaxial layer, at least two gate structures, and a shielding electrode structure. The trench structure includes a deep trench portion and two shallow trench portions respectively adjacent to two opposite sides of the deep trench portion. Each of the gate structures formed in each of the shallow trench portions includes a gate insulating layer and a gate electrode. The gate insulating layer has a first dielectric layer, a second dielectric layer and a third dielectric layer. The second dielectric layer is interposed between the first and third dielectric layers. Additionally, a portion of the gate insulating layer is in contact with a shielding dielectric layer of the shielding electrode structure.
    Type: Application
    Filed: January 13, 2016
    Publication date: July 13, 2017
    Inventors: PO-HSIEN LI, JIA-FU LIN, CHIA-CHENG CHEN, WEI-CHIEH LIN
  • Publication number: 20170171981
    Abstract: The present invention provides a substrate structure and a method of fabricating the substrate structure. The method includes: forming a first wiring layer on a first carrier, forming a dielectric layer on the first wiring layer, forming a second wiring layer on the dielectric layer, forming an insulating protection layer on the second wiring layer, forming a second carrier on the insulating protection layer, and removing the first carrier. The formation of the second carrier provides the substrate structure with adequate rigidity to avoid breakage or warpage such that the miniaturization requirement can be satisfied.
    Type: Application
    Filed: December 29, 2016
    Publication date: June 15, 2017
    Inventors: Chun-Hsien Lin, Shih-Chao Chiu, Yu-Cheng Pai, Tzu-Chieh Shen, Chia-Cheng Chen
  • Patent number: 9673140
    Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a laminate on the carrier, wherein the laminate has a built-up portion and a release portion smaller in size than the built-up portion, the release portion covering the bonding pads and the built-up portion being laminated on the release portion and the carrier; forming a plurality of conductive posts in the built-up portion; and removing the release portion and the built-up portion on the release portion such that a cavity is formed in the laminate to expose the bonding pads, the conductive posts being positioned around a periphery of the cavity. Therefore, the present invention has simplified processes.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: June 6, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chia-Cheng Chen, Ming-Chen Sun, Tzu-Chieh Shen, Shih-Chao Chiu, Wei-Chung Hsiao, Yu-Cheng Pai, Don-Son Jiang
  • Patent number: 9666302
    Abstract: An IC includes a memory core logic unit, an output unit, and an input unit. The memory logic unit is coupled to a plurality of bit cells configured to control read and write of data to and from the plurality of bit cells. The input unit is formed on the integrated circuit. The output unit is formed on the integrated circuit. The input unit includes a second plurality of multiplexers for signal selection, at least one lock up latch for storing data and configured to increase a hold time for the data, and at least one shadow latch configured to store a copy of the data stored in the at least one lock up latch. The output unit includes a first plurality of multiplexers for signal selection and at least one high phase pass latch for storing data.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hung Chang, Chia-Cheng Chen, Ching-Wei Wu
  • Publication number: 20170047240
    Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.
    Type: Application
    Filed: October 26, 2016
    Publication date: February 16, 2017
    Inventors: Yu-Cheng Pai, Chun-Hsien Lin, Shih-Chao Chiu, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Patent number: 9564346
    Abstract: A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: February 7, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen
  • Patent number: 9515188
    Abstract: An embodiment fin field-effect-transistor (finFET) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of the channel region. The gate oxide includes a thinnest portion having a first thickness and a thickest portion having a second thickness different than the first thickness. A difference between the first thickness and the second thickness is less than a maximum thickness variation, and the maximum thickness variation is in accordance with an operating voltage of the finFET.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: December 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chen, Meng-Shu Lin, Liang-Yin Chen, Xiong-Fei Yu, Hui-Cheng Chang, Syun-Ming Jang
  • Patent number: 9510463
    Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: November 29, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Cheng Pai, Chun-Hsien Lin, Shih-Chao Chiu, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Patent number: 9455025
    Abstract: A static random access memory (SRAM) including at least a memory cell array, a first data line connected to the memory cell array, and a read assist unit connected to the first data line. The read assist unit is configured to suppress a voltage level of the first data line during a read operation of the memory cell array.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: September 27, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Wei Wu, Ming-Hung Chang, Chia-Cheng Chen
  • Publication number: 20160218019
    Abstract: A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments.
    Type: Application
    Filed: April 1, 2016
    Publication date: July 28, 2016
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Chang SU, Shih-Fu HUANG, Chia-Cheng CHEN
  • Publication number: 20160181428
    Abstract: An embodiment fin field-effect-transistor (finFET) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of the channel region. The gate oxide includes a thinnest portion having a first thickness and a thickest portion having a second thickness different than the first thickness. A difference between the first thickness and the second thickness is less than a maximum thickness variation, and the maximum thickness variation is in accordance with an operating voltage of the finFET.
    Type: Application
    Filed: December 22, 2014
    Publication date: June 23, 2016
    Inventors: Chia-Cheng Chen, Meng-Shu Lin, Liang-Yin Chen, Xiong-Fei Yu, Hui-Cheng Chang, Syun-Ming Jang
  • Publication number: 20160163621
    Abstract: A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.
    Type: Application
    Filed: October 6, 2015
    Publication date: June 9, 2016
    Inventors: Shih-Chao Chiu, Chun-Hsien Lin, Yu-Cheng Pai, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Publication number: 20160099204
    Abstract: A package structure is provided, including: a board having a plurality of conductive traces; a plurality of conductive pads formed on the board and each having a height greater than a height of each of the conductive traces; and an electronic component disposed on and electrically connected to the conductive pads via a plurality of conductive elements, wherein at least one of the conductive traces is positioned in proximity of at least one of the conductive pads. Therefore, the conductive elements are prevented from being in contact with the conductive traces, and the problem that the conductive pads and the conductive traces are shorted is solved. The present invention further provides a method for fabricating the packaging substrate.
    Type: Application
    Filed: May 12, 2015
    Publication date: April 7, 2016
    Inventors: Chang-Fu Lin, Chin-Tsai Yao, Chia-Cheng Chen, Chih-Jen Yang, Fu-Tang Huang
  • Publication number: 20160081186
    Abstract: The present invention provides a substrate structure and a method of fabricating the substrate substrure. The method includes: forming a first wiring layer on a first carrier, forming a dielectric layer on the first wiring layer, forming a second wiring layer on the dielectric layer, forming an insulating protection layer on the second wiring layer, forming a second carrier on the insulative protection layer, and remvoing the first carrier. The formation of the second carrier provides the substrate structure with adequate rigidity to avoid breakage or warpage such that the miniaturization requirement can be satisfied.
    Type: Application
    Filed: January 28, 2015
    Publication date: March 17, 2016
    Inventors: Chun-Hsien Lin, Shih-Chao Chiu, Yu-Cheng Pai, Tzu-Chieh Shen, Chia-Cheng Chen
  • Publication number: 20160079151
    Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.
    Type: Application
    Filed: April 22, 2015
    Publication date: March 17, 2016
    Inventors: Shih-Chao Chiu, Chun-Hsien Lin, Yu-Cheng Pai, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Publication number: 20160079170
    Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.
    Type: Application
    Filed: May 10, 2015
    Publication date: March 17, 2016
    Inventors: Yu-Cheng Pai, Wei-Chung Hsiao, Shih-Chao Chiu, Chun-Hsien Lin, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Patent number: 9281311
    Abstract: An integrated circuit includes a plurality of metal layers of bit cells of a memory cell array disposed in a first metal layer and extending in a first direction, a plurality of word lines of the memory cell array disposed in a second metal layer and extending in a second direction that is different from the first direction, and at least two conductive traces disposed in a third metal layer substantially adjacent to each other and extending at least partially across the memory cell array, a first one of the at least two conductive traces coupled to a driving source node of a write assist circuit, and a second conductive trace of the at least two conductive traces coupled to an enable input of the write-assist circuit, where the at least two conductive traces form at least one embedded capacitor having a capacitive coupling to the bit line.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: March 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Wei Wu, Wei-Shuo Kao, Chia-Cheng Chen, Kuang Ting Chen
  • Publication number: 20160021743
    Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.
    Type: Application
    Filed: December 26, 2014
    Publication date: January 21, 2016
    Inventors: Yu-Cheng Pai, Chun-Hsien Lin, Shih-Chao Chiu, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen
  • Publication number: 20160013123
    Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a dielectric layer on the carrier; forming a plurality of conductive posts in the dielectric layer; and forming a cavity in the dielectric layer to expose the bonding pads, wherein the conductive posts are positioned around a periphery of the cavity, thereby simplifying the fabrication process.
    Type: Application
    Filed: December 8, 2014
    Publication date: January 14, 2016
    Inventors: Yu-Cheng Pai, Chun-Hsien Lin, Shih-Chao Chiu, Wei-Chung Hsiao, Ming-Chen Sun, Tzu-Chieh Shen, Chia-Cheng Chen