Patents by Inventor Chia-Cheng Chen

Chia-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140146631
    Abstract: One or more techniques for improving Vccmin for a dual port synchronous random access memory (DPSRAM) cell utilized as a single port synchronous random access memory (SPSRAM) cell are provided herein. In some embodiments, a second word line signal is sent to a second word line of the DPSRAM cell. For example, the second word line signal is sent in response to a logical low at a first bit line or a logical low at a second bit line. In this way, Vccmin is improved for the DPSRAM cell.
    Type: Application
    Filed: November 28, 2012
    Publication date: May 29, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ching-Wei Wu, Cheng Hung Lee, Chia-Cheng Chen
  • Publication number: 20140080316
    Abstract: A method of fabricating a semiconductor device includes contacting water with a silicon oxide layer. The method further includes diffusing an ozone-containing gas through water to treat the silicon oxide layer. The method further includes forming a dielectric layer over the treated silicon oxide layer.
    Type: Application
    Filed: November 15, 2013
    Publication date: March 20, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Liang-Gi YAO, Chia-Cheng CHEN, Clement Hsingjen WANN
  • Patent number: 8659936
    Abstract: A SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode. A SRAM comprising: at least one memory cell circuit, comprising a latch circuit with at least two inverters, and comprising two power receiving terminals for receiving power; and a power supplying circuit, for providing the power to the memory cell circuit, such that the voltages at the power receiving terminals of the latch circuit is below a predetermined voltage level when data is written to the latch circuit. In one embodiment, the memory cell circuit includes a plurality of data accessing terminals and the data accessing terminals are respectively controlled by at least two pass-transistor switch devices.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: February 25, 2014
    Assignees: Faraday Technology Corp., National Chiao Tung University
    Inventors: Ching-Te Chuang, Hao-I Yang, Mao-Chih Hsia, Wei Hwang, Chia-Cheng Chen, Wei-Chiang Shih
  • Publication number: 20140021636
    Abstract: A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.
    Type: Application
    Filed: September 23, 2013
    Publication date: January 23, 2014
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh, Ming Chiang Lee, Bernd Karl Appelt
  • Patent number: 8603924
    Abstract: A method of forming gate dielectric material includes forming a silicon oxide gate layer over a substrate. The silicon oxide gate layer is treated with a first ozone-containing gas. After treating the silicon oxide gate layer, a high dielectric constant (high-k) gate dielectric layer is formed over the treated silicon oxide gate layer.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: December 10, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Liang-Gi Yao, Chia-Cheng Chen, Clement Hsingjen Wann
  • Patent number: 8569894
    Abstract: A semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: October 29, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Chang Su, Shih-Fu Huang, Chia-Cheng Chen, Tzu-Hui Chen, Kuang-Hsiung Chen, Pao-Ming Hsieh, Ming Chiang Lee, Bernd Karl Appelt
  • Patent number: 8556220
    Abstract: A locking device for a display mounting assembly comprises, a base frame, two mounting racks and two locking members, wherein the assembly and disassembly of the mounting racks and the base frame can be easily achieved by a simple action of pulling and pressing of the locking members. Furthermore, it doesn't have to drill through holes and the elongated holes in the mounting racks, which consequently reduces manufacturing cost.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: October 15, 2013
    Assignees: Hi-Max Innovation Co., Ltd.
    Inventor: Chia-Cheng Chen
  • Publication number: 20130256244
    Abstract: A locking device for a display mounting assembly comprises: a base frame, two mounting racks and two locking members, wherein the assembly and disassembly of the mounting racks and the base frame can be easily achieved by a simple action of pulling and pressing of the locking members. Furthermore, it doesn't have to drill through holes and the elongated holes in the mounting racks, which consequently reduces manufacturing cost.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 3, 2013
    Inventor: Chia-Cheng CHEN
  • Patent number: 8399776
    Abstract: A substrate having single patterned metal layer includes a patterned base having at least a plurality of apertures, the patterned metal layer disposed on the patterned base, and a first surface finish layer. Parts of the lower surface of the patterned metal layer are exposed by the apertures of the patterned base to form a plurality of first contact pads for downward electrical connection externally, and parts of the upper surface of the patterned metal layer function as a plurality of second contact pads for upward electrical connection externally. The first surface finish layer is disposed at least on one or more surfaces of the second contact pads, and the first surface finish layer is wider than the second contact pad beneath. A package applied with the substrate disclosed herein further comprises at least a die conductively connected to the second contact pads of the substrate.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: March 19, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Bernd Karl Appelt, William T Chen, Calvin Cheung, Shih-Fu Huang, Yuan-Chang Su, Chia-Cheng Chen, Ta-Chun Lee
  • Publication number: 20130048811
    Abstract: The present invention is related to a mounting kit comprising a mother base, a son base and a connection unit. The mother base is disposed to a fixed object with a storage space to move up/down and/or turning left/right and fastened to a position of the fixed object. The son base is correspondingly connected to the storage space which permits the user to choose to move inward or outward and fastened to a position. The connection unit is correspondingly connected to the son base which to make up/down and or facing downward/upward adjustment and fastened to a position. Its front can be disassembled for fastening to the back of the display device or the back of the supporting object. Hence, the invention can steadfastly fasten different brands and different measurements of display devices to a fixed object (or its supporting rod), and adjust the best viewing angle for the user.
    Type: Application
    Filed: August 30, 2011
    Publication date: February 28, 2013
    Inventors: Yi-Chen TSENG, Chia-Cheng Chen
  • Patent number: 8367473
    Abstract: A chip package structure includes a substrate, a die, and a package body. The substrate includes a single patterned, electrically conductive layer, and a patterned dielectric layer adjacent to an upper surface of the electrically conductive layer. A part of a lower surface of the electrically conductive layer forms first contact pads for electrical connection externally. The patterned dielectric layer exposes a part of the upper surface of the electrically conductive layer to form second contact pads. The electrically conductive layer exposes the lower surface of the patterned dielectric layer on a lower periphery of the substrate. The die is electrically connected to the second contact pads, the patterned dielectric layer and the die being positioned on the same side of the electrically conductive layer. The package body is disposed adjacent to the upper surface of the electrically conductive layer and covers the patterned dielectric layer and the die.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: February 5, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Shih-Fu Huang, Yuan-Chang Su, Chia-Cheng Chen, Ta-Chun Lee, Kuang-Hsiung Chen
  • Patent number: 8345504
    Abstract: A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: January 1, 2013
    Assignees: Faraday Technology Corp., National Chiao Tung University
    Inventors: Ching-Te Chuang, Hao-I Yang, Yi-Wei Lin, Wei Hwang, Wei-Chiang Shih, Chia-Cheng Chen
  • Patent number: 8320164
    Abstract: A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: November 27, 2012
    Assignees: Faraday Technology Corp., National Chiao Tung University
    Inventors: Ching-Te Chuang, Hao-I Yang, Mao-Chih Hsia, Yung-Wei Lin, Chien-Yu Lu, Ming-Hsien Tu, Wei Hwang, Shyh-Jye Jou, Chia-Cheng Chen, Wei-Chiang Shih
  • Patent number: 8300420
    Abstract: A circuit substrate includes an electrically conductive layer having electrically conductive patterns formed therein, an insulating layer having a through hole, and a composite layer positioned between the electrically conductive layer and the insulating layer. The through hole is configured for having an electronic component mounted thereon. The composite layer includes a polymer matrix and at least one carbon nanotube bundle embedded in the polymer matrix. One end of the at least one carbon nanotube bundle contacts the electrically conductive patterns, and the other is exposed in the through hole of the insulation layer.
    Type: Grant
    Filed: May 24, 2009
    Date of Patent: October 30, 2012
    Assignee: Zhen Ding Technology Co., Ltd.
    Inventors: Chung-Jen Tsai, Hung-Yi Chang, Chia-Cheng Chen, Meng-Chieh Hsu, Cheng-Hsien Lin
  • Patent number: 8288869
    Abstract: A semiconductor package includes a substrate, a die, and a package body. The substrate includes: (a) a core including a resin reinforced with fibers; (b) a plurality of openings extending through the core; (c) a dielectric layer; and (d) a single conductive layer disposed between the dielectric layer and the core. Portions of a lower surface of the single conductive layer cover the plurality of openings to form a plurality of first contact pads for electrical connection external to the semiconductor package. Exposed portions of an upper surface of the single conductive layer form a plurality of second contact pads. The die is electrically connected to the plurality of second contact pads, and the package body encapsulates the die.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: October 16, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Shih-Fu Huang, Yuan-Chang Su, Chia-Cheng Chen, Kuang-Hsiung Chen, Ming-Chiang Lee, Bernd Karl Appelt, Chia-Hsiung Hsieh
  • Patent number: 8228752
    Abstract: A memory circuit includes a first memory array, a second memory array and a switch module, wherein the first memory array has a first node and a second node, the second memory array has a third node and a fourth node, the first node is coupled to a first supply voltage, and the fourth supply voltage is coupled to a second supply voltage smaller than the first supply voltage. The switch module is coupled to the second node, the third node, the first supply voltage and the second supply voltage. When the memory circuit is operated under an inactive mode, the switch module electrically connects the second node to the third node, electrically disconnects the second node from the second supply voltage, and electrically disconnects the third node from the first supply voltage.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: July 24, 2012
    Assignee: Faraday Technology Corp.
    Inventors: Hung-Yu Li, Wade Wang, Rick Zheng, James Ma, Kun-Ti Lee, Chia-Cheng Chen
  • Patent number: 8213257
    Abstract: A Random Access Memory (RAM) is provided. The RAM includes a plurality of word-line drivers, at least a first tracking transistor and a second tracking transistor. Each word-line driver has an input node receiving a decoding signal, a power node receiving an operation voltage and a driving node driving a word-line. In an embodiment, the first tracking transistor has two channel terminal nodes respectively coupled to the driving node of one of the word-line driver and a channel terminal node of the second tracking transistor; wherein the first tracking transistor has electronic characteristics tracking those of a driving transistor of word-line driver, and the second tracking transistor has electronic characteristics tracking those of pass-gate transistor(s) in each cell of the RAM.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: July 3, 2012
    Assignees: Faraday Technology Corp., National Chiao Tung University
    Inventors: Ching-Te Chuang, Yi-Wei Lin, Chia-Cheng Chen, Wei-Chiang Shih
  • Publication number: 20120094504
    Abstract: A method of forming gate dielectric material includes forming a silicon oxide gate layer over a substrate. The silicon oxide gate layer is treated with a first ozone-containing gas. After treating the silicon oxide gate layer, a high dielectric constant (high-k) gate dielectric layer is formed over the treated silicon oxide gate layer.
    Type: Application
    Filed: January 11, 2011
    Publication date: April 19, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Liang-Gi YAO, Chia-Cheng CHEN, Clement Hsingjen WANN
  • Publication number: 20120044779
    Abstract: A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation.
    Type: Application
    Filed: January 19, 2011
    Publication date: February 23, 2012
    Applicants: National Chiao Tung University, FARADAY TECHNOLOGY CORPORATION
    Inventors: Ching-Te Chuang, Hao-I Yang, Yi-Wei Lin, Wei Hwang, Wei-Chiang Shih, Chia-Cheng Chen
  • Patent number: D666029
    Type: Grant
    Filed: March 31, 2012
    Date of Patent: August 28, 2012
    Assignees: Hi-Max Innovation Co., Ltd.
    Inventor: Chia-Cheng Chen