Patents by Inventor Chia-Chi Chang

Chia-Chi Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11456246
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first dielectric material disposed over the device, and an opening is formed in the first dielectric material. The semiconductor device structure further includes a conductive structure disposed in the opening, and the conductive structure includes a first sidewall. The semiconductor device structure further includes a surrounding structure disposed in the opening, and the surrounding structure surrounds the first sidewall of the conductive structure. The surrounding structure includes a first spacer layer and a second spacer layer adjacent the first spacer layer. The first spacer layer is separated from the second spacer layer by an air gap.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20220293650
    Abstract: A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures in a first direction. The semiconductor device further includes a gate structure. The gate structure includes a top surface; a first sidewall angled at a non-perpendicular angle with respect to the top surface; and a second sidewall angled with respect to the top surface. The gate structure further includes a first horizontal surface extending between the first sidewall and the second sidewall, wherein the first horizontal surface is parallel to the top surface, and a dimension of the gate structure in a second direction, perpendicular to the first direction, is less than a dimension of each of the plurality of isolation structures in the second direction.
    Type: Application
    Filed: June 2, 2022
    Publication date: September 15, 2022
    Inventors: Chia-Yu WEI, Fu-Cheng CHANG, Hsin-Chi CHEN, Ching-Hung KAO, Chia-Pin CHENG, Kuo-Cheng LEE, Hsun-Ying HUANG, Yen-Liang LIN
  • Publication number: 20220293521
    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes an active region including a channel region and a source/drain region and extending along a first direction, and a source/drain contact structure over the source/drain region. The source/drain contact structure includes a base portion extending lengthwise along a second direction perpendicular to the first direction, and a via portion over the base portion. The via portion tapers away from the base portion.
    Type: Application
    Filed: February 28, 2022
    Publication date: September 15, 2022
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11439979
    Abstract: Provided is a method of making colloidal selenium nanoparticles. The method includes the steps as follows: Step (A): providing a reducing agent and an aqueous solution containing a selenium precursor; Step (B): mixing the aqueous solution containing the selenium precursor and the reducing agent to form a mixture solution in a reaction vessel and heating the mixture solution to undergo a reduction reaction and produce a composition containing selenium nanoparticles, residues and a gas, and guiding the gas out of the reaction vessel, wherein an amount of the residues is less than 20% by volume of the mixture solution; and Step (C): dispersing the selenium nanoparticles with a medium to obtain the colloidal selenium nanoparticles. The method has advantages of simplicity, safety, time-effectiveness, cost-effectiveness, high yield and eco-friendliness.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: September 13, 2022
    Assignee: TRIPOD NANO TECHNOLOGY CORPORATION
    Inventors: Chung-Jung Hung, Chun-Lun Chiu, Chia-Chi Chang, Hsin-Chang Huang, Teng-Chieh Hsu, Meng-Hsiu Chih, Jim-Min Fang
  • Publication number: 20220285494
    Abstract: A semiconductor structure includes a source/drain (S/D) feature; one or more channel semiconductor layers connected to the S/D feature; a gate structure engaging the one or more channel semiconductor layers; a first silicide feature at a frontside of the S/D feature; a second silicide feature at a backside of the S/D feature; and a dielectric liner layer at the backside of the S/D feature, below the second silicide feature, and spaced away from the second silicide feature by a first gap.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 8, 2022
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11410876
    Abstract: A method includes providing a structure having a substrate, a first dielectric layer over the substrate, one or more semiconductor channel layers over the first dielectric layer and connecting a first source/drain (S/D) feature and a second S/D feature, and a gate structure engaging the one or more semiconductor channel layers; etching the substrate from the backside of the structure to form a first trench exposing the first S/D feature and a second trench exposing the second S/D feature; forming an S/D contact in the first trench; etching at least a portion of the first dielectric layer resulting in a portion of the S/D contact protruding from the first dielectric layer at the backside of the structure; and depositing a seal layer over the S/D contact, wherein the seal layer caps an air gap between the gate structure and the seal layer.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chia-Hao Chang, Lin-Yu Huang, Li-Zhen Yu, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20220246740
    Abstract: A semiconductor structure includes a substrate; a first structure over the substrate and having a first gate stack and two first gate spacers on two opposing sidewalls of the first gate stack; a second structure over the substrate and having a second gate stack and two second gate spacers on two opposing sidewalls of the second gate stack; a source/drain (S/D) feature over the substrate and adjacent to the first and the second gate stacks; an S/D contact over the S/D feature and between one of the first gate spacers and one of the second gate spacers; a conductive via disposed over and electrically connected to the S/D contact; and a dielectric liner layer. A first portion of the dielectric liner layer is disposed on a sidewall of the one of the first gate spacers and is directly above the S/D contact and spaced from the S/D contact.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 4, 2022
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20220246464
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first conductive structure disposed over the device, and the first conductive structure includes a first sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer disposed on the first portion, a second conductive structure disposed adjacent the first conductive structure, and the second conductive structure includes a second sidewall having a third portion and a fourth portion. The semiconductor device structure further includes a second spacer layer disposed on the third portion, and an air gap is formed between the first conductive structure and the second conductive structure. The second portion, the first spacer layer, the fourth portion, and the second spacer layer are exposed to the air gap.
    Type: Application
    Filed: April 18, 2022
    Publication date: August 4, 2022
    Inventors: Lin-Yu HUANG, Li-Zhen YU, Chia-Hao CHANG, Cheng-Chi CHUANG, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20220238693
    Abstract: A semiconductor structure includes a substrate, a semiconductor layer, a gate stack, two first gate spacers over two opposing sidewalls of the gate stack and extending above the gate stack; a second gate spacer over a sidewall of one of the first gate spacers and having an upper portion over a lower portion; an etch stop layer adjacent to the lower portion and spaced away from the upper portion; and a seal layer over the gate stack, the two first gate spacers and the second gate spacer, resulting in a first void and a second void below the first seal layer. The first void is above the lower portion of the second gate spacer and laterally between the etch stop layer and the upper portion of the second gate spacer. The second void is above the gate stack and laterally between the two first gate spacers.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Inventors: Cheng-Chi Chuang, Lin-Yu Huang, Chia-Hao Chang, Yu-Ming Lin, Ting-Ya Lo, Chi-Lin Teng, Hsin-Yen Huang, Hai-Ching Chen
  • Patent number: 11398562
    Abstract: An apparatus is provided which comprises: a first stack comprising a magnetic insulating material (MI such as, EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene; a second stack comprising an MI material and a TMD, wherein the first and second stacks are separated by an insulating material (e.g., oxide); a magnet (e.g., a ferromagnet or a paramagnet) adjacent to the TMDs of the first and second stacks, and also adjacent to the insulating material; and a magnetoelectric material (e.g., (LaBi)FeO3, LuFeO3, PMN-PT, PZT, AlN, or (SmBi)FeO3) adjacent to the magnet.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: July 26, 2022
    Assignee: Intel Corporation
    Inventors: Chia-Ching Lin, Sasikanth Manipatruni, Tanay Gosavi, Sou-Chi Chang, Dmitri Nikonov, Ian A. Young
  • Patent number: 11380721
    Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: July 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Yu Wei, Fu-Cheng Chang, Hsin-Chi Chen, Ching-Hung Kao, Chia-Pin Cheng, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
  • Publication number: 20220202442
    Abstract: A computer-assisted needle insertion system and a computer-assisted needle insertion method are provided. The computer-assisted needle insertion method includes: obtaining a first machine learning (ML) model and a second ML model; obtaining a computed tomography (CT) image and a needle insertion path, generating a suggested needle insertion path according to the first ML model, the CT image, and the needle insertion path, and instructing a needle to approach a needle insertion point on a skin of a target, wherein the needle insertion point is located on the suggested needle insertion path; obtaining a breath signal of the target, and estimating whether a future breath state of the target is normal according to the second ML model and the breath signal; and outputting a suggested needle insertion period according to the breath signal in response to determining that the future breath state is normal.
    Type: Application
    Filed: November 23, 2021
    Publication date: June 30, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Po-An Hsu, Chih-Chi Chang, Chih-Wei Chien, Chia-Pin Li, Kun-Ta Wu, Wei-Zheng Lu
  • Patent number: 11373879
    Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.
    Type: Grant
    Filed: September 12, 2020
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Kai Chen, Ching-Hsiang Tsai, Kao-Feng Liao, Chih-Chieh Chang, Chun-Hao Kung, Fang-I Chih, Hsin-Ying Ho, Chia-Jung Hsu, Hui-Chi Huang, Kei-Wei Chen
  • Publication number: 20220152392
    Abstract: A method for generating stimulation parameters, an electrical stimulation control apparatus and an electrical stimulation system are provided. After receiving a brainwave signal, the brainwave signal is decomposed to obtain a first sub-signal and a second sub-signal. Then, the first sub-signal is analyzed to obtain an intrinsic frequency series, and the second sub-signal is converted to a Boolean signal. Subsequently, the intrinsic frequency series and the Boolean signal, which serve as a set of stimulation parameters, are outputted to the stimulator, enabling the stimulator to generate a stimulus signal.
    Type: Application
    Filed: November 19, 2020
    Publication date: May 19, 2022
    Applicant: A-Neuron Electronic Corporation
    Inventors: Chia-Chi Chang, Pei-Chen Lin, Cheng-Hsiang Cheng, Po-Huang Chen
  • Publication number: 20220083111
    Abstract: A wireless sensing system includes a power supply unit, a control unit, a backup power unit, and a wake-up unit. The control unit includes a microprocessor. The microprocessor acts according to a forced shutdown instruction and transmits the forced shutdown instruction to the wake-up unit through an internal control pin in order for the wake-up unit to generate a forced shutdown clock matching the forced shutdown instruction, transmit the forced shutdown clock to the power supply unit, and thereby stop the power supply unit from generating electricity, and for the backup power unit to transmit the electricity stored therein to the wake-up unit and thereby enable the wake-up unit to maintain its basic electrically driven functions. The backup power unit can supply a small amount of electricity to sustain the basic electrically driven functions of the system.
    Type: Application
    Filed: September 10, 2021
    Publication date: March 17, 2022
    Inventor: Chia-Chi CHANG
  • Publication number: 20220079371
    Abstract: Disclosed are a steam cooking apparatus (1) and a steam cooking method.
    Type: Application
    Filed: March 19, 2020
    Publication date: March 17, 2022
    Applicant: TEAM YOUNG TECHNOLOGY CO., LTD.
    Inventors: Pin-Chun Huang, Dy-Cheng Wang, Chia-Chi Chang
  • Patent number: 11275418
    Abstract: A wireless sensing system includes a power supply unit, a control unit, a backup power unit, and a wake-up unit. The control unit includes a microprocessor. The microprocessor acts according to a forced shutdown instruction and transmits the forced shutdown instruction to the wake-up unit through an internal control pin in order for the wake-up unit to generate a forced shutdown clock matching the forced shutdown instruction, transmit the forced shutdown clock to the power supply unit, and thereby stop the power supply unit from generating electricity, and for the backup power unit to transmit the electricity stored therein to the wake-up unit and thereby enable the wake-up unit to maintain its basic electrically driven functions. The backup power unit can supply a small amount of electricity to sustain the basic electrically driven functions of the system.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: March 15, 2022
    Assignee: CHAOYANG UNIVERSITY OF TECHNOLOGY
    Inventor: Chia-Chi Chang
  • Patent number: 11269234
    Abstract: A reflective display device includes a thin-film transistor (TFT) array substrate, a front panel laminate (FPL), a front protection sheet, a back protection sheet, a light blocking layer, and a light source. The front panel laminate is located on the TFT array substrate, and has a transparent conductive layer and a display medium layer. The display medium layer is located between the transparent conductive layer and the TFT array substrate. The front protection sheet is located on the front panel laminate. The back protection sheet is located below the TFT array substrate. The light blocking layer at least covers a lateral surface of the back protection sheet. The light source faces toward a lateral surface of the front panel laminate, a lateral surface of the TFT array substrate, and the lateral surface of the back protection sheet.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: March 8, 2022
    Assignee: E Ink Holdings Inc.
    Inventors: Chia-Chi Chang, Chih-Chun Chen, Chi-Ming Wu, Yi-Ching Wang, Jia-Hung Chen, Cheng-Hsien Lin
  • Patent number: 11227557
    Abstract: The present disclosure provides a display device. The display device includes a substrate, a pixel array, a circuit bridge structure, a first trace region, a second trace region, and a display film layer. The pixel array is located on the substrate. The circuit bridge structure is located at one side of the pixel array. The first trace region is located between the pixel array and a first side of the circuit bridge structure. The second trace region is located at a second side opposite to the first side. The display film layer is located on the pixel array, and an orthogonal projection of the display film layer on the substrate is spaced apart from an orthogonal projection of the circuit bridge structure on the substrate.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: January 18, 2022
    Assignee: E Ink Holdings Inc.
    Inventors: Chia-Chi Chang, Chih-Chun Chen, Chi-Ming Wu, Yi-Ching Wang, Jia-Hung Chen
  • Publication number: 20210394157
    Abstract: Provided is a method of making colloidal selenium nanoparticles. The method includes the steps as follows: Step (A): providing a reducing agent and an aqueous solution containing a selenium precursor; Step (B): mixing the aqueous solution containing the selenium precursor and the reducing agent to form a mixture solution in a reaction vessel and heating the mixture solution to undergo a reduction reaction and produce a composition containing selenium nanoparticles, residues and a gas, and guiding the gas out of the reaction vessel, wherein an amount of the residues is less than 20% by volume of the mixture solution; and Step (C): dispersing the selenium nanoparticles with a medium to obtain the colloidal selenium nanoparticles. The method has advantages of simplicity, safety, time-effectiveness, cost-effectiveness, high yield and eco-friendliness.
    Type: Application
    Filed: July 23, 2020
    Publication date: December 23, 2021
    Inventors: Chung-Jung HUNG, Chun-Lun CHIU, Chia-Chi CHANG, Hsin-Chang HUANG, Teng-Chieh HSU, Meng-Hsiu CHIH, Jim-Min FANG