Patents by Inventor Chia-Chi Huang

Chia-Chi Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160118239
    Abstract: The present disclosure provides A gate insulating layer comprising: a first silicon nitride film having a first thickness and a first content of N—H bonds; a second silicon nitride film having a second thickness and a second content of N—H bonds, disposed on the first silicon nitride film; and a third silicon nitride film having a third thickness and a third content of N—H bonds, disposed on the second silicon nitride film; wherein both the first thickness and the third thickness are less than the second thickness, both the N—H bonds in the first content and the third content are less than that in the second N—H bonds content, and a difference of the N—H bonds between the third content and the first content is no less than 5%. The present disclosure also provides a method for forming the above gate insulating layer.
    Type: Application
    Filed: January 6, 2016
    Publication date: April 28, 2016
    Inventors: Wei-ting CHEN, Chia-chi HUANG, Chunchieh HUANG, Youyuan HU
  • Publication number: 20150311350
    Abstract: A TFT array substrate and a manufacturing method of the same are disclosed by the present disclosure. The TFT array substrate includes a base, a light shielding layer, and a low hydrogen layer. The light shielding layer includes a silicon nitride layer formed on the base, and an amorphous silicon light shielding layer formed on the silicon nitride layer. The low hydrogen layer includes a silicon oxide layer formed on the amorphous silicon light shielding layer of the light shielding layer, and a low hydrogen Poly-Si layer formed on the silicon oxide layer. The layer number of the light shielding layer is equal to that of the low hydrogen layer. The time of manufacturing the light shielding layer matched that of manufacturing the low hydrogen layer, which enhances whole capacity of the TFT array substrate dramatically, and reduces risk of the manufacturing process.
    Type: Application
    Filed: January 30, 2015
    Publication date: October 29, 2015
    Inventors: Chia-chi HUANG, Min-ching HSU
  • Patent number: 9159773
    Abstract: A thin film transistor includes a semiconductor layer including a source region, a drain region, a channel region, first lightly doped drain regions adjacent to the channel region and second lightly doped drain regions adjacent to the first lightly doped drain regions; wherein the second lightly doped drain regions have a doping concentration lower than that of the first lightly doped drain regions. According to the present application, the leakage current in a switching transistor may be further reduced, thereby avoiding instability and even failure in the operation of the assembly caused by overlarge leakage current.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: October 13, 2015
    Assignee: EverDisplay Optronics (Shanghai) Limited
    Inventors: Chia-che Hsu, Chia-chi Huang, Wei-ting Chen, Min-ching Hsu
  • Publication number: 20150129989
    Abstract: The present disclosure provides A gate insulating layer comprising: a first silicon nitride film having a first thickness and a first content of N—H bonds; a second silicon nitride film having a second thickness and a second content of N—H bonds, disposed on the first silicon nitride film; and a third silicon nitride film having a third thickness and a third content of N—H bonds, disposed on the second silicon nitride film; wherein both the first thickness and the third thickness are less than the second thickness, both the N—H bonds in the first content and the third content are less than that in the second N—H bonds content, and a difference of the N—H bonds between the third content and the first content is no less than 5%. The present disclosure also provides a method for forming the above gate insulating layer.
    Type: Application
    Filed: August 19, 2014
    Publication date: May 14, 2015
    Inventors: Wei-ting CHEN, Chia-chi HUANG, Chunchieh HUANG, Youyuan HU
  • Patent number: 8962990
    Abstract: The disclosure provides a multilayer composition containing fluoropolymer and method for fabricating the same, and a solar cell module. The multilayer composition includes: a fluoropolymer layer; a non-fluorinated polymer layer; and an adhesion promoter layer formed between the fluoropolymer layer and the non-fluorinated polymer layer, wherein the adhesion promoter layer includes aromatic diamines or aromatic polyamines.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: February 24, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Tien-Shou Shieh, Chia-Chi Huang
  • Publication number: 20150011047
    Abstract: Methods for fabricating an IGZO layer and fabricating TFT are provided in the present invention. The method for fabricating TFT includes the following steps: (1) depositing an IGZO layer and forming a surface oxidizing gas protective layer on the IGZO layer; (2) coating the IGZO layer with a photoresist, and then subjecting the photoresist to an exposing and developing process to form a photoresist pattern; and (3) subjecting the IGZO layer to an etching process, and then removing the photoresist. By forming an oxidizing gas protective layer, the present methods for fabricating an IGZO layer and fabricating TFT can effectively reduce the effect of hydrogen atom on IGZO layer and avoid the change of IGZO layer from semiconductor to conductor, thereby improving the stability of the IGZO layer and thus the TFT, and reducing the negative bias of threshold voltage generated by the long-term continuous use of the device.
    Type: Application
    Filed: June 27, 2014
    Publication date: January 8, 2015
    Inventors: Chia-chi HUANG, Min-ching HSU, Hsueh-ming TSAI, Wen-xia ZUO
  • Publication number: 20140374714
    Abstract: A thin film transistor includes a semiconductor layer including a source region, a drain region, a channel region, first lightly doped drain regions adjacent to the channel region and second lightly doped drain regions adjacent to the first lightly doped drain regions; wherein the second lightly doped drain regions have a doping concentration lower than that of the first lightly doped drain regions. According to the present application, the leakage current in a switching transistor may be further reduced, thereby avoiding instability and even failure in the operation of the assembly caused by overlarge leakage current.
    Type: Application
    Filed: June 6, 2014
    Publication date: December 25, 2014
    Inventors: Chia-che HSU, Chia-chi HUANG, Wei-ting CHEN, Min-ching HSU
  • Publication number: 20140374718
    Abstract: The present application provides a thin film transistor, an active matrix organic light emitting diode assembly and a method for manufacturing the same. The thin film transistor includes: a substrate; a buffer layer on the substrate; a semiconductor layer on the buffer layer, including a source region, a drain region and a channel region; a first gate insulating layer covering the semiconductor layer; a second gate insulating layer foot on the first gate insulating layer, a width of the second gate insulating layer foot being smaller than a width of the first gate insulating layer; and a gate electrode on the second gate insulating layer foot; wherein a part of the first gate insulating layer that is on the semiconductor layer has a flat upper surface. The present application may obtain better implantation profiles of source region and drain region, thereby obtaining better uniformity in TFT performance.
    Type: Application
    Filed: June 19, 2014
    Publication date: December 25, 2014
    Inventors: Chia-Che HSU, Chia-Chi HUANG, Wei-Ting CHEN, Min-Ching HSU
  • Publication number: 20140361276
    Abstract: An active matrix organic light emitting diode assembly includes a substrate and a plurality of pixels on the substrate, each of the pixels at least includes an Organic Light Emitting Diode (OLED), a first Thin Film Transistor (TFT) and a second TFT, wherein: the second TFT is configured to drive the OLED; the first TFT is configured to drive the second TFT, the first TFT includes a buffer layer on the substrate, a semiconductor layer on the buffer layer, a gate insulating layer covering the semiconductor layer and a gate electrode on the gate insulating layer, and the semiconductor layer includes a source region and a drain region of first conductivity type and a bottom doped region of second conductivity type. The leakage current in AMOLED assembly may be suppressed, thereby avoiding instability and even failure of assembly operation caused by overlarge leakage current.
    Type: Application
    Filed: June 6, 2014
    Publication date: December 11, 2014
    Inventors: Chia-che HSU, Chia-chi HUANG, Min-ching HSU
  • Publication number: 20130068303
    Abstract: The disclosure provides a multilayer composition containing fluoropolymer and method for fabricating the same, and a solar cell module. The multilayer composition includes: a fluoropolymer layer; a non-fluorinated polymer layer; and an adhesion promoter layer formed between the fluoropolymer layer and the non-fluorinated polymer layer, wherein the adhesion promoter layer includes aromatic diamines or aromatic polyamines.
    Type: Application
    Filed: April 11, 2012
    Publication date: March 21, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Tien-Shou SHIEH, Chia-Chi HUANG
  • Patent number: 8367455
    Abstract: A fabricating method of an image sensor includes the steps of: providing a substrate; forming sensing elements on the substrate; forming microlenses on the sensing elements; filling a stuffed material on the microlenses, and air regions are formed in the stuffed material; and forming optical filters on the stuffed material.
    Type: Grant
    Filed: May 30, 2010
    Date of Patent: February 5, 2013
    Assignee: Himax Imaging, Inc.
    Inventors: Yu-Ping Hu, Chih-Wei Hsiung, Fang-Ming Huang, Chia-Chi Huang, Chung-Wei Chang
  • Patent number: 8331477
    Abstract: A progressive parallel interference canceller (PPIC) and a method and a receiver thereof are illustrated. The PPIC reconstructs each subchannel interference reconstruction signal through several iterations and subtracts the corresponding subchannel interference reconstruction signal from each subchannel frequency-domain reception signal to obtain a subchannel frequency-domain signal. Thereby, according to the present disclosure, inter-channel interference can be cancelled without re-performing channel coding or estimating the signal to noise ratio (SNR) or frequency offset.
    Type: Grant
    Filed: September 7, 2009
    Date of Patent: December 11, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Chao-Wang Huang, Pang-An Ting, Jiun-Yo Lai, Chia-Chi Huang
  • Patent number: 8306143
    Abstract: A system and method of transmit diversity for wireless communication. The system includes a transmitting terminal having a plurality of transmission antennas and a receiving terminal having a plurality of receiving antennas. The method includes analyzing channel state information obtained by the transmitting terminal; selecting an antenna to be one in use from the receiving antennas; matching the selected antenna in use with the wireless signals that are to be transmitted; transmitting wireless signals that are matched to the receiving terminal for being calculated and determining the pre-selected antenna in use, thereby significantly reducing complexities of the receiving terminal.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: November 6, 2012
    Assignee: National Chiao Tung University
    Inventors: Chun-Ying Ma, Chia-Chi Huang
  • Publication number: 20110299616
    Abstract: A system and method of transmit diversity for wireless communication. The system includes a transmitting terminal having a plurality of transmission antennas and a receiving terminal having a plurality of receiving antennas. The method includes analyzing channel state information obtained by the transmitting terminal; selecting an antenna to be one in use from the receiving antennas; matching the selected antenna in use with the wireless signals that are to be transmitted; transmitting wireless signals that are matched to the receiving terminal for being calculated and determining the pre-selected antenna in use, thereby significantly reducing complexities of the receiving terminal.
    Type: Application
    Filed: July 21, 2010
    Publication date: December 8, 2011
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: CHUN-YING MA, CHIA-CHI HUANG
  • Publication number: 20110291211
    Abstract: A fabricating method of an image sensor includes the steps of: providing a substrate; forming sensing elements on the substrate; forming microlenses on the sensing elements; filling a stuffed material on the microlenses, and air regions are formed in the stuffed material; and forming optical filters on the stuffed material.
    Type: Application
    Filed: May 30, 2010
    Publication date: December 1, 2011
    Inventors: Yu-Ping Hu, Chih-Wei Hsiung, Fang-Ming Huang, Chia-Chi Huang, Chung-Wei Chang
  • Publication number: 20110149063
    Abstract: The present invention provides a measurement device and a measurement method of double-sided optical films, wherein the device and the method make use of an illumination light source with well-designed bright fields and dark fields and a device with double-sided coincidence optics to obtain the variation information about the horizontal mismatch and the angular mismatch of double-sided optical films.
    Type: Application
    Filed: September 8, 2010
    Publication date: June 23, 2011
    Applicant: Industrial Technology Research Institute
    Inventors: SHU-PING DONG, HUNG-MING TAI, DEH-MING SHYU, CHI-TANG CHEN, CHING-MING YEH, YI-CHANG CHEN, CHIA-CHI HUANG
  • Patent number: 7939906
    Abstract: A manufacturing method for an electron tomography specimen with embedded fiducial markers includes the following steps. A chip of wafer is provided. The chip includes at least one inspecting area. At least one trench is produced beside the inspecting area. A liquid with the markers is filled into the trenches. A first protection layer is coated on the chip, and then a second protection layer is deposited on the first protection layer. Therefore, the markers can be embedded into the electron tomography specimen. The embedded markers can improve the alignment process, due to those embedded markers are easily tracked during feature tracking procedure. In addition, our novel invention also successfully provides a modified version of the technique to deposit gold beads onto TEM pillar samples for much improved 3D reconstruction.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: May 10, 2011
    Assignee: Inotera Memories, Inc.
    Inventors: Jian-Shing Luo, Chia-Chi Huang
  • Publication number: 20110013735
    Abstract: A progressive parallel interference canceller (PPIC) and a method and a receiver thereof are illustrated. The PPIC reconstructs each subchannel interference reconstruction signal through several iterations and subtracts the corresponding subchannel interference reconstruction signal from each subchannel frequency-domain reception signal to obtain a subchannel frequency-domain signal. Thereby, according to the present disclosure, inter-channel interference can be cancelled without re-performing channel coding or estimating the signal to noise ratio (SNR) or frequency offset.
    Type: Application
    Filed: September 7, 2009
    Publication date: January 20, 2011
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chao-Wang Huang, Pang-An Ting, Jiun-Yo Lai, Chia-Chi Huang
  • Publication number: 20100084555
    Abstract: A manufacturing method for an electron tomography specimen with embedded fiducial markers includes the following steps. A chip of wafer is provided. The chip includes at least one inspecting area. At least one trench is produced beside the inspecting area. A liquid with the markers is filled into the trenches. A first protection layer is coated on the chip, and then a second protection layer is deposited on the first protection layer. Therefore, the markers can be embedded into the electron tomography specimen. The embedded markers can improve the alignment process, due to those embedded markers are easily tracked during feature tracking procedure. In addition, our novel invention also successfully provides a modified version of the technique to deposit gold beads onto TEM pillar samples for much improved 3D reconstruction.
    Type: Application
    Filed: May 26, 2009
    Publication date: April 8, 2010
    Applicant: INOTERA MEMORIES, INC.
    Inventors: JIAN-SHING LUO, CHIA-CHI HUANG
  • Publication number: 20080211997
    Abstract: A polarizing plate is provided. The polarizing plate includes a polarizing film, a first protective film and a second protective film respectively disposed on both sides of the polarizing film, and a polyimide optical compensation film having thickness direction retardation (Rth) or both, in-plane retardation (R0) and thickness direction retardation (Rth) disposed on the first protective film. The invention also provides a liquid crystal display including the polarizing plate.
    Type: Application
    Filed: February 8, 2008
    Publication date: September 4, 2008
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shih-Ming Chen, Chyi-Ming Leu, Tzong-Ming Lee, Young-Jen Lee, Chia-Chi Huang, Chi-Fu Tseng