Patents by Inventor Chia-Chieh Lin
Chia-Chieh Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10096515Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.Type: GrantFiled: July 8, 2013Date of Patent: October 9, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chih-Hui Huang, Sheng-Chau Chen, Shih-Pei Chou, Chia-Chieh Lin
-
Patent number: 10056353Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.Type: GrantFiled: December 19, 2013Date of Patent: August 21, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Chia-Chieh Lin, U-Ting Chen
-
Publication number: 20180226449Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.Type: ApplicationFiled: April 3, 2018Publication date: August 9, 2018Inventors: Shih Pei Chou, Hung-Wen Hsu, Ching-Chung Su, Chun-Han Tsao, Chia-Chieh Lin, Shu-Ting Tsai, Jiech-Fun Lu, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
-
Patent number: 9941320Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.Type: GrantFiled: March 21, 2016Date of Patent: April 10, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih Pei Chou, Hung-Wen Hsu, Ching-Chung Su, Chun-Han Tsao, Chia-Chieh Lin, Shu-Ting Tsai, Jiech-Fun Lu, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
-
Patent number: 9553020Abstract: A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers.Type: GrantFiled: July 27, 2016Date of Patent: January 24, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Shih Pei Chou, U-Ting Chen, Chia-Chieh Lin
-
Publication number: 20160336231Abstract: A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers.Type: ApplicationFiled: July 27, 2016Publication date: November 17, 2016Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Shih Pei Chou, U-Ting Chen, Chia-Chieh Lin
-
Patent number: 9406712Abstract: A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers.Type: GrantFiled: May 29, 2015Date of Patent: August 2, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Shih Pei Chou, U-Ting Chen, Chia-Chieh Lin
-
Publication number: 20160204154Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.Type: ApplicationFiled: March 21, 2016Publication date: July 14, 2016Inventors: Shih Pei Chou, Hung-Wen Hsu, Ching-Chung Su, Chun-Han Tsao, Chia-Chieh Lin, Shu-Ting Tsai, Jiech-Fun Lu, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
-
Patent number: 9360755Abstract: Among other things, one or more techniques and systems for performing a spin coating process associated with a wafer and for controlling thickness of a photoresist during the spin coating process are provided. In particular, a thickening phase is performed during the spin coating process in order to increase a thickness of the photoresist. For example, air temperature of down flow air, flow speed of the down flow air, and heat temperature of heat supplied towards the wafer are increased during the thickening phase. The increase in down flow air and heat increase a vaporization factor of the photoresist, which results in an increase in viscosity and thickness of the photoresist. In this way, the wafer can be rotated at relatively lower speeds, while still attaining a desired thickness. Lowering rotational speed of wafers allows for relatively larger wafers to be stably rotated.Type: GrantFiled: March 14, 2013Date of Patent: June 7, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chun-Wei Chang, Chia-Chieh Lin, Chih-Chien Wang, Wang-Pen Mo, Hung-Chang Hsieh
-
Publication number: 20150287757Abstract: A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers.Type: ApplicationFiled: May 29, 2015Publication date: October 8, 2015Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Shih Pei Chou, U-Ting Chen, Chia-Chieh Lin
-
Patent number: 9076715Abstract: A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers.Type: GrantFiled: November 26, 2013Date of Patent: July 7, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Shih Pei Chou, U-Ting Chen, Chia-Chieh Lin
-
Publication number: 20150179613Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.Type: ApplicationFiled: December 19, 2013Publication date: June 25, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Chia-Chieh Lin, U-Ting Chen
-
Publication number: 20140264709Abstract: A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers.Type: ApplicationFiled: November 26, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Shih Pei Chou, U-Ting Chen, Chia-Chieh Lin
-
Publication number: 20140264929Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.Type: ApplicationFiled: July 8, 2013Publication date: September 18, 2014Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chih-Hui Huang, Sheng-Chau Chen, Shih-Pei Chou, Chia-Chieh Lin
-
Publication number: 20140272704Abstract: Among other things, one or more techniques and systems for performing a spin coating process associated with a wafer and for controlling thickness of a photoresist during the spin coating process are provided. In particular, a thickening phase is performed during the spin coating process in order to increase a thickness of the photoresist. For example, air temperature of down flow air, flow speed of the down flow air, and heat temperature of heat supplied towards the wafer are increased during the thickening phase. The increase in down flow air and heat increase a vaporization factor of the photoresist, which results in an increase in viscosity and thickness of the photoresist. In this way, the wafer can be rotated at relatively lower speeds, while still attaining a desired thickness. Lowering rotational speed of wafers allows for relatively larger wafers to be stably rotated.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Inventors: Chun-Wei Chang, Chia-Chieh Lin, Chih-Chien Wang, Wang-Pen Mo, Hung-Chang Hsieh
-
Publication number: 20140119058Abstract: A power voltage conversion system for a controller integrated circuit includes a DC-to-DC converter and a controller IC. The DC-to-DC converter receivers an external DC voltage and the DC-to-DC converter at least has an inductance element and a switch element. The inductance element has at least one first winding and one second winding and the first winding is connected to the second winding in series. The controller IC is electrically connected to the inductance element and the switch element. The external DC voltage is converted into at least one power voltage according to a turn ratio between the first winding and the second winding, thus supplying power to the controller IC to control the switch element.Type: ApplicationFiled: October 30, 2012Publication date: May 1, 2014Applicant: Chicony Power Technology Co., Ltd.Inventors: Keng-Yi CHOU, Chia-Chieh LIN
-
Publication number: 20130162339Abstract: A compensating device is used for providing current compensation of an IC when operating in the high-voltage. The current compensating device includes a detecting unit, a rectifier, a filtering unit and a switching unit. The detecting unit electrically connected to an AC voltage. The rectifier is electrically connected to the detecting unit. The filtering unit is electrically connected to the rectifier. The switching unit is electrically connected to the filtering unit. The switching unit is conducted and provides a current to the IC when the AC voltage is above a predetermined voltage.Type: ApplicationFiled: December 24, 2011Publication date: June 27, 2013Inventors: Chao-Wei TSAI, Chia-Chieh LIN
-
Patent number: 8461908Abstract: A compensating device is used for providing current compensation of an IC when operating in the high-voltage. The current compensating device includes a detecting unit, a rectifier, a filtering unit and a switching unit. The detecting unit electrically connected to an AC voltage. The rectifier is electrically connected to the detecting unit. The filtering unit is electrically connected to the rectifier. The switching unit is electrically connected to the filtering unit. The switching unit is conducted and provides a current to the IC when the AC voltage is above a predetermined voltage.Type: GrantFiled: December 24, 2011Date of Patent: June 11, 2013Assignee: Chicony Power Technology Co., Ltd.Inventors: Chao-Wei Tsai, Chia-Chieh Lin
-
Publication number: 20120277182Abstract: An Anoectochilus spp. polysaccharide extract for stimulating the growth of advantageous bacteria, stimulating the release of granulocyte colony-stimulating factor (G-CSF), modulating T helper cell type I (Th1 cell), and/or modulating T helper cell type II (Th2 cell) is provided. The extract comprises an effective amount of a type II arabinogalactan of Anoectochilus spp. Also provided are a method for the preparation of the Anoectochilus spp. polysaccharide extract and the use of the extract.Type: ApplicationFiled: July 11, 2012Publication date: November 1, 2012Applicant: CHINA MEDICAL UNIVERSITYInventors: Wen-Chuan LIN, Chang-Chi HSIEH, Ting-Jang LU, Hsin-Sheng TSAY, Li-Chan YANG, Chia-Chieh LIN, Chung-Huang WANG
-
Publication number: 20120112643Abstract: A light-emitting diode lamp with multi-channel constant-voltage and constant-current control is disclosed. The light-emitting diode lamp includes a constant-current controller, a feedback controller, a constant-voltage controller, a plurality of light-emitting diode apparatuses, a plurality of first feedback components, and a plurality of second feedback components. The constant-current controller, the feedback controller, and the constant-voltage controller are used to process current signals and voltage signals fed back from the light-emitting diode apparatuses to provide an adaptive multi-channel constant-voltage and constant-current control, thus increasing overall efficiency and operation flexibility of the light-emitting diode lamp under the alternating current or direct current power supply.Type: ApplicationFiled: November 5, 2010Publication date: May 10, 2012Inventor: Chia-Chieh LIN