Patents by Inventor Chia-Chin LEE
Chia-Chin LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240363627Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.Type: ApplicationFiled: July 9, 2024Publication date: October 31, 2024Inventors: Kuan-Chang Chiu, Chia-Ching Lee, Chien-Hao Chen, Hung-Chin Chung, Hsien-Ming Lee, Chi On Chui, Hsuan-Yu Tung, Chung-Chiang Wu
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Publication number: 20240363424Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.Type: ApplicationFiled: July 11, 2024Publication date: October 31, 2024Inventors: Chung-Chiang Wu, Hsin-Han Tsai, Wei-Chin Lee, Chia-Ching Lee, Hung-Chin Chung, Cheng-Lung Hung, Da-Yuan Lee
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Publication number: 20240353819Abstract: A process-management system and a process-management method are provided. The process-management system includes a process-planning module, a process-management module, and a process-executing module. The process-planning module stores a preset workflow and is configured to receive a first input instruction and a second input instruction. The process-planning module provides the preset workflow according to the first input instruction, and adjusts the preset workflow according to the second input instruction to generate a customized workflow. The process-management module is electrically connected to the process-planning module and is configured to generate a work instruction according to the preset workflow or the customized workflow. The process-executing module is electrically connected to the process-management module and configured to process a workpiece according to the work instruction.Type: ApplicationFiled: April 24, 2023Publication date: October 24, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Po-Hsun WU, Xiao-Yi SU, Chia-Chin CHUANG, Chien-Yi LEE, Shao-Ku HUANG
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Patent number: 12087767Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.Type: GrantFiled: December 20, 2022Date of Patent: September 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Chang Chiu, Chia-Ching Lee, Chien-Hao Chen, Hung-Chin Chung, Hsien-Ming Lee, Chi On Chui, Hsuan-Yu Tung, Chung-Chiang Wu
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Patent number: 12087637Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.Type: GrantFiled: December 14, 2020Date of Patent: September 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Chiang Wu, Hsin-Han Tsai, Wei-Chin Lee, Chia-Ching Lee, Hung-Chin Chung, Cheng-Lung Hung, Da-Yuan Lee
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Patent number: 12074206Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.Type: GrantFiled: August 30, 2021Date of Patent: August 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Wei Chen, Chih-Yu Hsu, Hui-Chi Chen, Shan-Mei Liao, Jian-Hao Chen, Cheng-Hao Hou, Huang-Chin Chen, Cheng Hong Yang, Shih-Hao Lin, Tsung-Da Lin, Da-Yuan Lee, Kuo-Feng Yu, Feng-Cheng Yang, Chi On Chui, Yen-Ming Chen
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Patent number: 12050783Abstract: A method for performing table management of a memory device in a predetermined communications architecture with aid of table error correction and associated apparatus are provided. The method may include: utilizing the memory controller to perform a table error correction procedure to manage at least one table regarding internal management of the memory device, for example: when any error of any table page occurs, searching for a first parity identifier backward, and searching for a second parity identifier forward; selecting a next page of a page storing the first parity identifier to be a first page, selecting a page storing the second parity identifier to be a last page, and preparing at least a set of pages among multiple RAID-protection pages, for being decoded; and performing a RAID decoding operation on the set of pages to generate a recovered table page to be a replacement of the any table page.Type: GrantFiled: March 23, 2023Date of Patent: July 30, 2024Assignee: Silicon Motion, Inc.Inventors: Jie-Hao Lee, Chia-Chin Hsieh, Chian-Wen Chiu
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Patent number: 12040235Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.Type: GrantFiled: July 21, 2022Date of Patent: July 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
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Publication number: 20220276696Abstract: Example embodiments are provided related to a multi-engine asynchronous virtual reality system within which vestibular-ocular conflicts are reduced or eliminated. In an example embodiment, an apparatus detects, via a first processor, one or more positional coordinates from one or more virtual reality devices. The apparatus further detects, via the first processor, one or more movement parameters associated with a virtual reality rendering. The apparatus, upon determining, via a second processor and based at least in part on simulation of the one or more positional coordinates and the movement parameters, that one or more movement parameter of the one or more movement parameters exceeds a first physical movement threshold, further adjusts, via the first processor, periphery occlusion associated with the virtual reality rendering.Type: ApplicationFiled: February 26, 2021Publication date: September 1, 2022Inventors: Gabe Brown, Chia Chin Lee
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Publication number: 20170179544Abstract: A lithium positive electrode material is provided, which includes a host material and a doping material doped into the host material, wherein the doping material has a chemical formula of LiyLazZrwAluO12+(u*3/2), wherein 5?y?8, 2?z?5, 1?w?3, and 0<u<1. The lithium positive electrode material may collocate with carbon material and binder to form a positive electrode for a lithium battery.Type: ApplicationFiled: November 9, 2016Publication date: June 22, 2017Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hsiu-Fen LIN, Shih-Chieh LIAO, Chia-Chin LEE, Chi-Ju CHENG, Jin-Ming CHEN
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Publication number: 20170062125Abstract: A method for manufacturing a coil loading board includes following steps: providing a first plate configured single-side adhesive and double-side adhesive on both sides thereof; defining a first slot, a first through hole, a first connection hole and a groove through both sides of the first plate; providing a second plate configured double-die adhesive on a side thereof; forming a second slot, a second through hole and a second connection hole through both sides of the second plate; fixing the first plate and the second plate together; removing the single-side adhesive of the first plate.Type: ApplicationFiled: October 13, 2015Publication date: March 2, 2017Inventor: Chia-Chin LEE
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Publication number: 20160064990Abstract: A near field communication and wireless charging device includes a main body, a electronic circuit, a NFC module, a wireless charging module coupled to the electronic circuit. The NFC module and the wireless charging module are arranged independently. Further included a electrical connector, a first end of the electrical connector is coupled to the electronic circuit and a second end of the electrical connector is extending to outside of the main body to attaching to the electrical device bendingly.Type: ApplicationFiled: April 14, 2015Publication date: March 3, 2016Inventors: YUNG-PING LIN, QIU-RI ZHANG, CHIA-CHIN LEE
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Publication number: 20150188110Abstract: A battery with a heat-resistant layer is provided. The battery with a heat-resistant layer includes a positive electrode, a negative electrode, a separator, an electrolyte and a heat-resistant layer. The separator is disposed between the positive electrode and the negative electrode. The heat-resistant layer is disposed between at least one of the positive or negative electrodes and the separator, wherein the heat-resistant layer has a tetrapod-shaped surface morphology. The positive electrode, the negative electrode, the separator and the heat-resistant layer are soaked in the electrolyte. A method for manufacturing the heat-resistant layer is also provided.Type: ApplicationFiled: December 15, 2014Publication date: July 2, 2015Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hsiu-Fen LIN, Shih-Chieh LIAO, Chia-Ming CHANG, Min-Ling HOU, Yu-Hao HUANG, Chia-Chin LEE