Patents by Inventor Chia-Ching Huang

Chia-Ching Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240055026
    Abstract: A storage drive assembly is provided. The storage drive assembly includes a storage drive sized and shaped for insertion into a slot within a chassis, a latching mechanism coupled to a first end of the storage drive, the latching mechanism including an actuation component actuable to transition the latching mechanism from a locked state in which the latching mechanism restricts displacement of the storage drive relative to the chassis to an unlocked state in which the latching mechanism enables displacement of the storage drive assembly relative to the chassis, and a drive secure cover plate adapted to removably mate with the latching mechanism in the locked state, the mated drive secure cover plate preventing physical access to the actuation component.
    Type: Application
    Filed: August 15, 2022
    Publication date: February 15, 2024
    Inventors: Wu-Shu LIN, Fredrick Anthony CONSTANTINO, Kevin Jay LANGSTON, Chia-Ching HUANG
  • Patent number: 11790955
    Abstract: A storage drive assembly is provided. The storage drive assembly includes a storage drive sized and shaped for insertion into a slot within a chassis, a latching mechanism coupled to a first end of the storage drive, the latching mechanism including an actuation component actuable to transition the latching mechanism from a locked state in which the latching mechanism restricts displacement of the storage drive relative to the chassis to an unlocked state in which the latching mechanism enables displacement of the storage drive assembly relative to the chassis, and a drive secure cover plate adapted to removably mate with the latching mechanism in the locked state, the mated drive secure cover plate preventing physical access to the actuation component.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: October 17, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Wu-Shu Lin, Fredrick Anthony Constantino, Kevin Jay Langston, Chia-Ching Huang
  • Publication number: 20230282645
    Abstract: A semiconductor device includes an insulating layer, a semiconductor layer, and a compound semiconductor stacked layer disposed on a substrate in sequence, a first transistor, a second transistor, an isolation structure, and a conductive structure. The first transistor is disposed in a first device region and on the compound semiconductor stacked layer. The second transistor is disposed in a second device region and on the compound semiconductor stacked layer. The isolation structure is disposed between the first and second transistors. The conductive structure is disposed in the second device region, passes through the compound semiconductor stacked layer, and electrically connects the semiconductor layer to a second source of the second transistor. There is no electrical connection between the semiconductor layer in the first device region and a first source of the first transistor.
    Type: Application
    Filed: March 2, 2022
    Publication date: September 7, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Walter Wohlmuth, Shin-Cheng Lin, Chia-Ching Huang
  • Patent number: 11747987
    Abstract: An electronic device includes a data storage device and a host device. The host device is coupled to the data storage device via a predetermined interface and includes a processor. The processor dynamically adjusts a data transfer speed of the predetermined interface according to a data processing speed required by data to be read from or written to the data storage device.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: September 5, 2023
    Assignee: Silicon Motion, Inc.
    Inventors: Fu-Jen Shih, Chia-Ching Huang
  • Patent number: 11670708
    Abstract: A semiconductor device is provided, including a substrate, a seed layer on the substrate, an epitaxial layer on the seed layer, an electrode structure on the epitaxial layer and an electric field modulation structure. The electrode structure includes a gate structure, a source structure and a drain structure, wherein the source structure and the drain structure are positioned on opposite sides of the gate structure. The electric field modulation structure includes an electric connection structure and a conductive layer electrically connected to the electric connection structure. The conductive layer is positioned between the gate structure and the drain structure. The electric connection structure is electrically connected to the source structure and the drain structure.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: June 6, 2023
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng Lin, Chih-Yen Chen, Chia-Ching Huang
  • Publication number: 20230170389
    Abstract: A high electron mobility transistor includes a substrate, a compound semiconductor stacked layer, a cap layer, a gate electrode, a source electrode, a drain electrode, and a buried electrode and/or a conductive structure. The substrate has an active area. The cap layer is disposed on the compound semiconductor stacked layer. The gate electrode is disposed on the cap layer and extends along a first direction. The source electrode and the drain electrode are disposed on the compound semiconductor stacked layer, respectively on two sides of the gate electrode, and arranged along a second direction, where the first direction is perpendicular to the second direction. The conductive structure and/or the buried electrode passes through the compound semiconductor stacked layer and surrounds or lies in the active area, where the conductive structure and/or the buried electrode has a constant electric potential or is grounded.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 1, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng Lin, Chia-Ching Huang
  • Patent number: 11664430
    Abstract: A semiconductor device includes a compound semiconductor layer disposed on a substrate, a protection layer disposed on the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device also includes a plurality of field plates disposed over the protection layer and between the gate electrode and the drain electrode, wherein the plurality of field plates are separated from each other.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: May 30, 2023
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hsin-Chih Lin, Chang-Xiang Hung, Chia-Ching Huang, Yung-Hao Lin, Chia-Hao Lee
  • Publication number: 20220293779
    Abstract: A high electron mobility transistor includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate field plate, a source electrode, at least one first field plate, and a second field plate. The gate field plate is disposed on the semiconductor barrier layer. The source electrode is disposed on one side of the gate field plate, and the first field plate is disposed on the other side of the gate field plate and laterally spaced apart from the gate field plate. The second field plate covers the gate field plate and the first field plate and is electrically connected to the source electrode, where the area of the second field plate is larger than the sum of the area of the gate field plate and the area of the first field plate when perceived from a top-down perspective.
    Type: Application
    Filed: March 15, 2021
    Publication date: September 15, 2022
    Inventors: Yang Du, Shin-Chen Lin, Chia-Ching Huang
  • Patent number: 11398546
    Abstract: A semiconductor device is provided. The semiconductor device includes a channel layer disposed over a substrate, a barrier layer disposed over the channel layer, a compound semiconductor layer disposed over the barrier layer, a gate electrode disposed over the compound semiconductor layer, and a source electrode and a drain electrode disposed on opposite sides of the gate electrode. The source electrode and the drain electrode penetrate through at least a portion of the barrier layer. The semiconductor device also includes a source field plate connected to the source electrode through a source contact. The semiconductor device further includes a first electric field redistribution pattern disposed on the barrier layer and directly under the edge of the source field plate.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: July 26, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chun-Yi Wu, Chih-Yen Chen, Chang-Xiang Hung, Chia-Ching Huang
  • Publication number: 20220190475
    Abstract: A frequency reconfigurable phased array system comprises a signal generator outputting a power signal with an adjustable frequency, a plurality of radio frequency (RF) modules receiving the power signal, a control module generating excitation mode parameter sets and material processing event sets, a first database storing the excitation mode parameter sets, and a second database storing the material processing event sets. The control module generates a material processing schedule by selecting one of the material processing event sets based on a material recipe, an average power, and a total time of a material, and controls a signal frequency of the signal generator according to the material processing schedule and the excitation mode parameter sets, and a RF phase and a RF power of each of the RF modules, to have the RF modules generating a power signal.
    Type: Application
    Filed: December 28, 2020
    Publication date: June 16, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Joseph Poujiong WANG, Chia Ching HUANG, Wei-Ji CHEN, Yueh-Lin TSAI
  • Publication number: 20220159797
    Abstract: A microwave heating method includes following steps: setting multiple microwave heating modes and their corresponding arrangements of resonator; selecting one of the microwave heating modes according to a heating condition; and, disposing an object to be heated and at least one resonator into a heating chamber, and providing a microwave signal to heat the object to heated, wherein a resonance frequency of the at least one resonator is corresponding to a frequency of the microwave signal, and the at least one resonator is arranged in the arrangement corresponding to the selected microwave heating mode. A microwave heating device suitable for the above microwave heating method is also proposed.
    Type: Application
    Filed: December 24, 2020
    Publication date: May 19, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Chia-Ching Huang, Yueh-Lin Tsai, Wei-Ji Chen, Joseph Poujiong Wang
  • Patent number: 11316040
    Abstract: A high electron mobility transistor includes a channel layer, a barrier layer, a first compound semiconductor layer, and a second compound semiconductor layer. The channel layer is disposed on the substrate, and the barrier layer is disposed on the channel layer. The first compound semiconductor layer is disposed on the barrier layer. The second compound semiconductor layer is disposed between the barrier layer and the first compound semiconductor layer, where the first compound semiconductor layer and the second compound semiconductor layer include a concentration distribution of metal dopant, and the concentration distribution of metal dopant includes a first peak in the first compound semiconductor layer and a second peak in the second compound semiconductor layer.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: April 26, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Franky Juanda Lumbantoruan, Chia-Ching Huang, Chih-Yen Chen
  • Publication number: 20220102541
    Abstract: A semiconductor device is provided, including a substrate, a seed layer on the substrate, an epitaxial layer on the seed layer, an electrode structure on the epitaxial layer and an electric field modulation structure. The electrode structure includes a gate structure, a source structure and a drain structure, wherein the source structure and the drain structure are positioned on opposite sides of the gate structure. The electric field modulation structure includes an electric connection structure and a conductive layer electrically connected to the electric connection structure. The conductive layer is positioned between the gate structure and the drain structure. The electric connection structure is electrically connected to the source structure and the drain structure.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng LIN, Chih-Yen CHEN, Chia-Ching HUANG
  • Publication number: 20220085196
    Abstract: A high electron mobility transistor includes a channel layer, a barrier layer, a first compound semiconductor layer, and a second compound semiconductor layer. The channel layer is disposed on the substrate, and the barrier layer is disposed on the channel layer. The first compound semiconductor layer is disposed on the barrier layer. The second compound semiconductor layer is disposed between the barrier layer and the first compound semiconductor layer, where the first compound semiconductor layer and the second compound semiconductor layer include a concentration distribution of metal dopant, and the concentration distribution of metal dopant includes a first peak in the first compound semiconductor layer and a second peak in the second compound semiconductor layer.
    Type: Application
    Filed: September 14, 2020
    Publication date: March 17, 2022
    Inventors: Franky Juanda Lumbantoruan, Chia-Ching Huang, Chih-Yen Chen
  • Patent number: 11201234
    Abstract: A high-electron mobility transistor (HEMT) includes a substrate, a group III-V channel layer, a group III-V barrier layer, a group III-V cap layer, a source electrode, a first drain electrode, a second drain electrode, and a connecting portion. The group III-V channel layer, the group III-V barrier layer, and the group III-V cap layer are sequentially disposed on the substrate. The source electrode is disposed at one side of the group III-V cap layer, and the first and second drain electrodes are disposed at another side of the group III-V cap layer. The bottom surface of the first drain electrode is separated from the bottom surface of the second drain electrode, and the composition of the first drain electrode is different from the composition of the second drain electrode. The connecting portion is electrically coupled to the first drain electrode and the second drain electrode.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: December 14, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chia-Ching Huang, Chih-Yen Chen, Chun-Yi Wu, Chih-Jen Hsiao
  • Publication number: 20210305143
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a base, a seed layer, a compound semiconductor layer, a gate structure, a source structure, a drain structure, and a conductive paste. The seed layer is disposed on the base. The compound semiconductor layer is disposed on the seed layer. The gate structure is disposed on the compound semiconductor layer. The source structure and the drain structure are disposed on both sides of the gate structure. In addition, the conductive paste is disposed between the base and a lead frame, and the conductive paste extends to the side surface of the base.
    Type: Application
    Filed: March 24, 2020
    Publication date: September 30, 2021
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Yen CHEN, Hsin-Chang TSAI, Chun-Yi WU, Chia-Ching HUANG, Chih-Jen HSIAO, Wei-Chan CHANG, Francois HEBERT
  • Patent number: 11133246
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a base, a seed layer, a compound semiconductor layer, a gate structure, a source structure, a drain structure, and a conductive paste. The seed layer is disposed on the base. The compound semiconductor layer is disposed on the seed layer. The gate structure is disposed on the compound semiconductor layer. The source structure and the drain structure are disposed on both sides of the gate structure. In addition, the conductive paste is disposed between the base and a lead frame, and the conductive paste extends to the side surface of the base.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: September 28, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Yen Chen, Hsin-Chang Tsai, Chun-Yi Wu, Chia-Ching Huang, Chih-Jen Hsiao, Wei-Chan Chang, Francois Hebert
  • Publication number: 20210257466
    Abstract: A semiconductor device includes a compound semiconductor layer disposed on a substrate, a protection layer disposed on the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device also includes a plurality of field plates disposed over the protection layer and between the gate electrode and the drain electrode, wherein the plurality of field plates are separated from each other.
    Type: Application
    Filed: May 6, 2021
    Publication date: August 19, 2021
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsin-Chih LIN, Chang-Xiang HUNG, Chia-Ching HUANG, Yung-Hao LIN, Chia-Hao LEE
  • Patent number: 11089707
    Abstract: Embodiments disclosed herein provide an apparatus to enable smooth and safe assembly of functional modules to computer chassis. The apparatus includes a chassis and a pair of racks mounted to the chassis. Each rack has a plurality of gear teeth formed thereon. A module having a housing is slidably coupled to the chassis and disposed between the pair of racks. A pair of gear pinions are rotatably mounted to the housing and meshed to the gear teeth of one of the racks. A damping member is coupled between each gear pinion and the housing. A sliding movement of the housing relative to the chassis rotates the pair of gear pinions to roll over along the gear teeth. During the sliding movement of the housing, the damping member exerts a resistance force against the housing, to reduce the movement speed of the housing.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: August 10, 2021
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Chang-Hsing Lee, Chia-Ching Huang, Ta-Wei Chen, Sung-Feng Chen, Ming Jie Chai
  • Patent number: 11043563
    Abstract: A semiconductor device includes a compound semiconductor layer disposed on a substrate, a protection layer disposed on the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device also includes a plurality of field plates disposed over the protection layer and between the gate electrode and the drain electrode, wherein the plurality of field plates are separated from each other. A method for fabricating the semiconductor device is also provided.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: June 22, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hsin-Chih Lin, Chang-Xiang Hung, Chia-Ching Huang, Yung-Hao Lin, Chia-Hao Lee