Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.

Abstract: A processing method of a single crystal material includes the following steps. A single crystal material is provided as an object to be modified. The amorphous phase modification apparatus is used for emitting a femtosecond laser beam to process an internal portion of the object to be modified. The processing includes using a femtosecond laser beam to form a plurality of processing lines in the internal portion of the object to be modified, wherein each of the processing lines include a zigzag pattern processing, and a processing line spacing between the plurality of processing lines is in a range of 200 ?m to 600 ?m, wherein after the object to be modified is processed, a modified layer is formed in the object to be modified. Slicing or separating out a portion in the object to be modified that includes the modified layer.

Abstract: A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.

Abstract: A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.

Abstract: A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.

Abstract: A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.

Abstract: A plural-fans driving apparatus is provided to drive a first fan and a second fan, and the first fan and the second fan are three-phase fans. The plural-fans driving apparatus includes a controller, a first three-phase motor driver structure, a second three-phase motor driver structure, and a protection and input interface circuit. The protection and input interface circuit is coupled to the first three-phase motor driver structure and the second three-phase motor driver structure, and protects the first three-phase motor driver structure and the second three-phase motor driver structure. The controller controls the first three-phase motor driver structure to drive the first fan, and controls the second three-phase motor driver structure to drive the second fan.

Abstract: A plural-fans driving apparatus is provided to drive a first fan and a second fan, and the first fan and the second fan are three-phase fans. The plural-fans driving apparatus includes a controller, a first three-phase motor driver structure, a second three-phase motor driver structure, and a protection and input interface circuit. The protection and input interface circuit is coupled to the first three-phase motor driver structure and the second three-phase motor driver structure, and protects the first three-phase motor driver structure and the second three-phase motor driver structure. The controller controls the first three-phase motor driver structure to drive the first fan, and controls the second three-phase motor driver structure to drive the second fan.

Abstract: A plural-fans driving apparatus is provided to drive a first fan and a second fan, and the first fan and the second fan are three-phase fans. The plural-fans driving apparatus includes a controller, a first three-phase motor driver structure, a second three-phase motor driver structure, and a protection and input interface circuit. The protection and input interface circuit is coupled to the first three-phase motor driver structure and the second three-phase motor driver structure, and protects the first three-phase motor driver structure and the second three-phase motor driver structure. The controller controls the first three-phase motor driver structure to drive the first fan, and controls the second three-phase motor driver structure to drive the second fan.

Abstract: A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.

Abstract: A fan frame includes a housing, a shaft tube, a circuit board and a plurality of light-emitting elements. The housing includes a base and a plurality of connection members located between the base and a peripheral wall of the housing. The shaft tube is mounted on the base. The circuit board is mounted in the housing and includes a body having a through-hole. The circuit board is fit around the shaft tube via the through-hole and is integrally formed with a plurality of protruding ribs and at least one outer rib. Each protruding rib is aligned with a respective connection member. Each outer rib is located between two adjacent protruding ribs. The light-emitting elements are mounted on the protruding ribs and the outer rib. A fan including the fan frame is also disclosed.

Abstract: A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.

Abstract: A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a gate spacer on a sidewall of the dummy gate stack, removing the dummy gate stack to form an opening, forming a replacement gate stack in the opening, recessing the replacement gate stack to form a recess, filling the recess with a conductive material, and performing a planarization to remove excess portions of the conductive material over the gate spacer. A remaining portion of the conductive material forms a gate contact plug. A top portion of the gate contact plug is at a same level as a top portion of the first gate spacer.

Abstract: A semiconductor device and method of manufacture are provided in which an the physical characteristics of a dielectric material are modified in order to provide additional benefits to surrounding structures during further processing. The modification may be performed by implanting ions into the dielectric material to form a modified region. Once the ions have been implanted, further processing relies upon the modified structure of the modified region instead of the original structure.

Abstract: A reversible headwear (100), such as a beanie, includes a reversible headwear body (110) and a pom-pom (150) connected thereto. The reversible headwear body (110) is adjustable between a first configuration and a second configuration. The headwear body (110) has a first surface (112) and an opposite second surface (114). The first and second surfaces (112, 114) correspond to outer and inner surfaces respectively in the first configuration of the headwear body (110), and to the inner and outer surfaces respectively in the second configuration of the headwear body (110). The headwear body (110) has a through-hole (130) extending from the first surface (112) to the second surface (114).

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having reduced trench loading effect. The present disclosure provides a novel multi-layer cap film incorporating one or more oxygen-based layers for reducing trench loading effects in semiconductor devices. The multi-layer cap film can be made of a metal hard mask layer and one or more oxygen-based layers. The metal hard mask layer can be formed of titanium nitride (TiN). The oxygen-based layer can be formed of tetraethyl orthosilicate (TEOS).

Abstract: An interconnect structure and a method of forming are provided. The method includes forming an opening in a dielectric layer and an etch stop layer, wherein the opening extends only partially through the etch stop layer. The method also includes creating a vacuum environment around the device. After creating the vacuum environment around the device, the method includes etching through the etch stop layer to extend the opening and expose a first conductive feature. The method also includes forming a second conductive feature in the opening.

Abstract: A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.

Abstract: A fan includes a fan frame, an impeller, a plurality of blades and a light emitting unit. The impeller is rotatably coupled with the fan frame and includes a light diffuser ring. The plurality of blades is connected to the light diffuser ring. The light emitting unit is mounted in the fan frame, includes a board and plurality of light-emitting elements mounted on the board, and shines light on the light diffuser ring.