Patents by Inventor Chia-Han Lai

Chia-Han Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11532503
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pin-Wen Chen, Chia-Han Lai, Mei-Hui Fu, Min-Hsiu Hung, Ya-Yi Cheng
  • Publication number: 20220366161
    Abstract: A device detecting system is provided. The device detecting system includes a bar code scanner, a plurality of device accommodating spaces, a screen, and a server. The server obtains bar code information via the bar code scanner and opens one of the device accommodating spaces based on the bar code information to accommodate an electronic device. The server performs a test procedure on the electronic device to generate a test result, and displays the test result and operation information corresponding to the test result on the screen.
    Type: Application
    Filed: May 5, 2022
    Publication date: November 17, 2022
    Inventors: Chien-Chih CHANG, Pei-Yin CHEN, Wei-Han LIN, Bo-Rong CHU, Yen-Ting LIU, Yu-Shen MAI, Kuan-Yu HSIAO, Chia-Hsien LIN, Pei-Yu LIAO, Chun-Yen LAI, Sheng-Yi CHEN
  • Publication number: 20220359324
    Abstract: An electronic package is provided, in which an electronic component with a conductive layer on an outer surface thereof is embedded in an encapsulant, where at least one electrode pad is disposed on an active surface of the electronic component, and at least one wire electrically connected to the electrode pad is arranged inside the electronic component, so that the conductive layer is electrically connected to the wire, such that the electrode pad, the wire and the conductive layer are used as a power transmission structure which serves as a current path to reduce DC resistance and improve an impedance issue associated with the supply of power.
    Type: Application
    Filed: July 6, 2021
    Publication date: November 10, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Ho-Chuan Lin, Min-Han Chuang, Chia-Chu Lai
  • Publication number: 20220359975
    Abstract: An electronic package is provided, in which a ground layer is arranged on one side of an insulator, and a first antenna portion and a second antenna portion embedded in the insulator are vertically disposed on the ground layer, where a gap is formed between the first antenna portion and the second antenna portion, such that the first antenna portion and the second antenna portion are electrically matched with each other, and the ground layer is electrically connected to the second antenna portion but free from being electrically connected to the first antenna portion.
    Type: Application
    Filed: June 28, 2021
    Publication date: November 10, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chia-Chu Lai, Ho-Chuan Lin, Min-Han Chuang
  • Publication number: 20220359374
    Abstract: An electronic module is provided, in which a first metal layer, an insulating layer and a second metal layer are sequentially formed on side faces and a non-active face of an electronic component to serve as a capacitor structure, where the capacitor structure is exposed from an active face of the electronic component so that by directly forming the capacitor structure on the electronic component, a distance between the capacitor structure and the electronic component is minimized, such that the effect of suppressing impedance can be optimized.
    Type: Application
    Filed: September 2, 2021
    Publication date: November 10, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Ho-Chuan Lin, Chia-Chu Lai, Min-Han Chuang
  • Publication number: 20220338038
    Abstract: A method performed by a user equipment (UE) is provided. In the method, at least one of a first configuration associated with a first operation of switching a search space set group and a second configuration associated with a second operation of skipping a physical downlink control channel monitoring are received. Downlink control information comprising a specific field associated with at least one of the first configuration and the second configuration is also received. When the first and second configurations are received, the first operation is performed based on a value in the specific field and the first configuration when the value in the specific field is one of a first set of values, and the second operation is performed based on the value in the specific field and the second configuration when the value in the specific field is one of a second set of values.
    Type: Application
    Filed: April 8, 2022
    Publication date: October 20, 2022
    Inventors: CHIA-HSIN LAI, HSIN-HSI TSAI, HAI-HAN WANG, YUNG-LAN TSENG
  • Publication number: 20220335745
    Abstract: The present invention provides a display device, which includes a frame having an accommodating cavity and a display module disposed in the accommodating cavity. The display module includes a first light source, an optical unit, an imaging unit arranged on a side of the optical unit facing away from the first light source, and a lens array arranged on a side of the imaging unit facing away from the first light source. Corresponding to a preset pattern, light emitted by the first light source passes through the optical unit, the imaging unit and the lens array to form a default floating image in a floating display area outside the accommodating cavity. In addition, the present invention also provides a non-contact key and an input device including the above display module.
    Type: Application
    Filed: April 13, 2022
    Publication date: October 20, 2022
    Inventors: YU JEN LAI, YA HAN KO, YU-MING HUANG, CHIA TSUN HUANG
  • Publication number: 20220330215
    Abstract: A method and a user equipment of search space monitoring are provided. The method includes: receiving first configured information corresponding to a plurality of search space set groups, wherein a number of the plurality of search space set groups is greater than two; receiving a downlink control information (DCI) which includes a DCI field with a value indicating a first search space set group in the plurality of search space set groups according to the first configured information; and monitoring for a physical downlink control channel in a search space set in response to the search space set being included in the first search space set group.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 13, 2022
    Applicant: FG Innovation Company Limited
    Inventors: Chia-Hsin Lai, Hsin-Hsi Tsai, Hai-Han Wang
  • Publication number: 20220293503
    Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 15, 2022
    Inventors: Chun-Hsien HUANG, Peng-Fu HSU, Yu-Syuan TSAI, Min-Hsiu HUNG, Chen-Yuan KAO, Ken-Yu CHANG, Chun-I TSAI, Chia-Han LAI, Chih-Wei CHANG, Ming-Hsing TSAI
  • Patent number: 11444028
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY Ltd.
    Inventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
  • Patent number: 11387201
    Abstract: A chip package includes a semiconductor substrate, a supporting element, an antenna layer, and a redistribution layer. The semiconductor substrate has an inclined sidewall and a conductive pad that protrudes from the inclined sidewall. The supporting element is located on the semiconductor substrate, and has a top surface facing away from the semiconductor substrate, and has an inclined sidewall adjoining the top surface. The antenna layer is located on the top surface of the supporting element. The redistribution layer is located on the inclined sidewall of the supporting element, and is in contact with a sidewall of the conductive pad and an end of the antenna.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: July 12, 2022
    Assignee: XINTEC INC.
    Inventors: Po-Han Lee, Chia-Ming Cheng, Jiun-Yen Lai, Ming-Chung Chung, Wei-Luen Suen
  • Publication number: 20210193517
    Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.
    Type: Application
    Filed: March 8, 2021
    Publication date: June 24, 2021
    Inventors: Pin-Wen Chen, Chia-Han Lai, Chih-Wei Chang, Mei-Hui Fu, Ming-Hsing Tsai, Wei-Jung Lin, Yu-Shih Wang, Ya-Yi Cheng, I-Li Chen
  • Publication number: 20210074580
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.
    Type: Application
    Filed: November 23, 2020
    Publication date: March 11, 2021
    Inventors: Pin-Wen Chen, Chia-Han Lai, Mei-Hui Fu, Min-Hsiu Hung, Ya-Yi Cheng
  • Patent number: 10943823
    Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pin-Wen Chen, Chia-Han Lai, Chih-Wei Chang, Mei-Hui Fu, Ming-Hsing Tsai, Wei-Jung Lin, Yu Shih Shih Wang, Ya-Yi Cheng, I-Li Chen
  • Patent number: 10847411
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pin-Wen Chen, Chia-Han Lai, Mei-Hui Fu, Min-Hsiu Hung, Ya-Yi Cheng
  • Patent number: 10804140
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pin-Wen Chen, Chia-Han Lai, Mei-Hui Fu, Min-Hsiu Hung, Ya-Yi Cheng
  • Publication number: 20200118935
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Hong-Mao LEE, Huicheng CHANG, Chia-Han LAI, Chi-Hsuan NI, Cheng-Tung LIN, Huang-Yi HUANG, Chi-Yuan CHEN, Li-Ting WANG, Teng-Chun TSAI, Wei-Jung LIN
  • Publication number: 20200051858
    Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.
    Type: Application
    Filed: October 16, 2019
    Publication date: February 13, 2020
    Inventors: Pin-Wen Chen, Chia-Han Lai, Chih-Wei Chang, Mei-Hui Fu, Ming-Hsing Tsai, Wei-Jung Lin, Yu Shih Shih Wang, Ya-Yi Cheng, I-Li Chen
  • Publication number: 20190385904
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.
    Type: Application
    Filed: August 30, 2019
    Publication date: December 19, 2019
    Inventors: Pin-Wen Chen, Chia-Han Lai, Mei-Hui Fu, Min-Hsiu Hung, Ya-Yi Cheng
  • Patent number: 10510664
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin