Patents by Inventor Chia-hao Lee

Chia-hao Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11942542
    Abstract: A semiconductor device includes a substrate, a gate dielectric layer, a gate electrode, a field plate, a source electrode and a drain electrode. The gate dielectric layer is disposed on the substrate and includes a first portion having a first thickness, a second portion having a second thickness, and a third portion having a third thickness. The first, second and third thicknesses are different from each other, and the first thickness is smaller than the second and third thicknesses. The gate electrode is disposed on the first portion of the gate dielectric layer. The field plate is separated from and electrically coupled to the gate electrode, and is disposed on the second and third portions of the gate dielectric layer. The source and drain electrodes are disposed on the sides of the gate electrode and the field plate, respectively.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: March 26, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Syed-Sarwar Imam, Chia-Hao Lee, Chih-Hung Lin, Kun-Han Lin
  • Publication number: 20240096987
    Abstract: A semiconductor device includes an epitaxial layer, at least one gate trench, and at least one trench gate structure. The gate trench includes a lower gate trench and an upper gate trench, and a width of the lower gate trench is less than a width of the upper gate trench. The trench gate structure is disposed in the gate trench, and the trench gate structure includes a bottom gate structure, a middle gate structure, and a top gate structure. The thickness of the second gate dielectric layer of the middle gate structure is less than the thickness of the first gate dielectric layer of the bottom gate structure. The thickness of the third gate dielectric layer of the top gate structure is less than the thickness of the second gate dielectric layer of the middle gate structure. The first, second, and third gate electrodes are separated from each other.
    Type: Application
    Filed: September 18, 2022
    Publication date: March 21, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Syed-Sarwar Imam, Chih-Cherng Liao, Chia-Hao Lee
  • Publication number: 20240097050
    Abstract: A semiconductor device includes a trench disposed in an epitaxial layer on a substrate. A gate structure is disposed in the trench and includes upper and lower conductive portions. A dielectric isolation portion is disposed between the upper and lower conductive portions. A dielectric liner is disposed in the trench and has an opening on the bottom surface of the trench. The opening is filled up with a part of the lower conductive portion. A portion of the epitaxial layer and the lower conductive portion construct a Schottky barrier diode. A doped region is disposed in the epitaxial layer, under the bottom surface of the trench and on one side of the lower conductive portion. The portion of the epitaxial layer and a portion of the doped region are in contact with the lower conductive portion.
    Type: Application
    Filed: September 18, 2022
    Publication date: March 21, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chen-Dong Tzou, Chih-Cherng Liao, Chia-Hao Lee
  • Patent number: 11933809
    Abstract: The present application discloses an inertial sensor comprising a proof mass, an anchor, a flexible member and several sensing electrodes. The anchor is positioned on one side of the sensing, mass block in a first axis. The flexible member is connected to the anchor point and extends along the first axis towards the proof mass to connect the proof mass, in which the several sensing electrodes are provided. In this way, the present application can effectively solve the problems of high difficulty in the production and assembly of inertial sensors and poor product reliability thereof.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: March 19, 2024
    Assignee: SENSORTEK TECHNOLOGY CORP.
    Inventors: Shih-Wei Lee, Chia-Hao Lin, Shih-Hsiung Tseng, Kuan-Ju Tseng, Chao-Shiun Wang
  • Publication number: 20240084447
    Abstract: A sealing article includes a body and a coating layer disposed on at least one surface of the body. The body comprises a polymeric elastomer such as perfluoroelastomer or fluoroelastomer. The coating layer comprises at least one metal. The sealing article may be a seal, a gasket, an O-ring, a T-ring or any other suitable product. The sealing article is resistant to ultra-violet (UV) light and plasma, and may be used for sealing a semiconductor processing chamber.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Peng-Cheng Hong, Jun-Liang Pu, W.L. Hsu, Chung-Hao Kao, Chia-Chun Hung, Cheng-Yi Wu, Chin-Szu Lee
  • Patent number: 11920238
    Abstract: A method of making a sealing article that includes a body and a coating layer disposed on at least one surface of the body. The body comprises a polymeric elastomer such as perfluoroelastomer or fluoroelastomer. The coating layer comprises at least one metal. The sealing article may be a seal, a gasket, an O-ring, a T-ring or any other suitable product. The sealing article is resistant to ultra-violet (UV) light and plasma, and may be used for sealing a semiconductor processing chamber.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Peng-Cheng Hong, Jun-Liang Pu, W. L. Hsu, Chung-Hao Kao, Chia-Chun Hung, Cheng-Yi Wu, Chin-Szu Lee
  • Patent number: 11923409
    Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
  • Publication number: 20230207682
    Abstract: A semiconductor device, including: a substrate having a first conductive type, an epitaxial layer disposed on the substrate, a doped region disposed in the epitaxial layer, and a gate electrode disposed through the doped region and extending into the epitaxial layer. The epitaxial layer has the first conductive type, and the doped region has a second conductive type different from the first conductive type. The gate electrode includes a first structure having a first dimension, and a second structure above the first structure. The second structure includes a main portion and a protruding portion below the main portion, wherein the main portion has a second dimension larger than the first dimension, and the protruding portion has the first dimension.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Syed-Sarwar IMAM, Chia-Hao LEE
  • Patent number: 11664430
    Abstract: A semiconductor device includes a compound semiconductor layer disposed on a substrate, a protection layer disposed on the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device also includes a plurality of field plates disposed over the protection layer and between the gate electrode and the drain electrode, wherein the plurality of field plates are separated from each other.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: May 30, 2023
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hsin-Chih Lin, Chang-Xiang Hung, Chia-Ching Huang, Yung-Hao Lin, Chia-Hao Lee
  • Publication number: 20230100115
    Abstract: A semiconductor device includes a substrate, a gate dielectric layer, a gate electrode, a field plate, a source electrode and a drain electrode. The gate dielectric layer is disposed on the substrate and includes a first portion having a first thickness, a second portion having a second thickness, and a third portion having a third thickness. The first, second and third thicknesses are different from each other, and the first thickness is smaller than the second and third thicknesses. The gate electrode is disposed on the first portion of the gate dielectric layer. The field plate is separated from and electrically coupled to the gate electrode, and is disposed on the second and third portions of the gate dielectric layer. The source and drain electrodes are disposed on the sides of the gate electrode and the field plate, respectively.
    Type: Application
    Filed: September 29, 2021
    Publication date: March 30, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Syed-Sarwar Imam, Chia-Hao Lee, Chih-Hung Lin, Kun-Han Lin
  • Publication number: 20230024109
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a first doped region formed in the substrate, a second doped region formed in the substrate and surrounding the first doped region, and a plurality of strip third doped regions formed in the substrate and located underneath the first doped region and the second doped region. In addition, the first doped region has a doping type which is the opposite of that of the second doped region. The strip third doped region has a doping type which is the same as that of the second doped region.
    Type: Application
    Filed: October 6, 2022
    Publication date: January 26, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shih-Chieh CHIEN, Chia-Hao LEE, Din-Ru YANG, Chia-Shen LIU
  • Publication number: 20220253528
    Abstract: The present disclosure provides a system and a method of fileless malware detection, and the method of the fileless malware detection includes steps as follows. The execution of the writable section in the memory is intercepted; the executable code corresponding to the execution is extracted from the writable section; whether the executable code is malicious is analyzed.
    Type: Application
    Filed: March 24, 2021
    Publication date: August 11, 2022
    Inventors: Fu-Hau HSU, Teng-Chuan HSIAO, Chia-Hao LEE
  • Patent number: 11348997
    Abstract: A semiconductor device includes a substrate, an epitaxial layer, an emitter region, and a collector region. The epitaxial layer is disposed over the substrate and has a first conductivity type. The drift region is disposed in the epitaxial layer and has a second conductivity type that is the opposite of the first conductivity type. The emitter region is disposed in the epitaxial layer outside the drift region. The collector region is disposed in the drift region. The semiconductor device also includes a doped region. The doped region is disposed adjacent to the bottom surface of the drift region and has the first conductivity type.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 31, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Ankit Kumar, Chia-Hao Lee
  • Patent number: 11299581
    Abstract: The present invention discloses a conjugated polymer, which is a random copolymer, and with Formula I: Additionally, the present invention also discloses an organic photovoltaic device comprising the conjugated polymer.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 12, 2022
    Assignee: RAYNERGY TEK INC.
    Inventors: Chuang-Yi Liao, Wei-Long Li, Chia-Hao Lee
  • Publication number: 20210343837
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of strip first doped regions formed in the substrate, a plurality of strip second doped regions formed in the substrate and respectively located between the strip first doped regions, a third doped region formed in the substrate and surrounding the strip first doped regions and the strip second doped regions, and a fourth doped region formed in the substrate and located underneath the strip first doped regions, the strip second doped regions and the third doped region. The doping type of the strip first doped region is the opposite of that of the strip second doped region. The doping type of the third doped region is the same as that of the strip second doped region. The doping type of the fourth doped region is the same as that of the strip second doped region.
    Type: Application
    Filed: May 1, 2020
    Publication date: November 4, 2021
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shih-Chieh CHIEN, Chia-Hao LEE, Din-Ru YANG, Chia-Shen LIU
  • Patent number: 11158723
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a first well region, a second well region, an isolation structure, and a gate structure. The first well region is disposed in the substrate. The second well region is disposed in the substrate. The second well region is adjoining the first well region. The isolation structure is disposed in the first well region. The gate structure is disposed on the substrate. The gate structure includes a first gate portion and a second gate portion. The first gate portion overlaps the first well region and the second well region. There is an opening between the first gate portion and the second gate portion exposing a portion of the isolation structure.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: October 26, 2021
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chih-Hung Lin, Chia-Hao Lee
  • Patent number: 11127847
    Abstract: A semiconductor device includes a compound semiconductor layer disposed over a substrate, a protection layer disposed over the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode which penetrate through the protection layer and are disposed on the compound semiconductor layer. The semiconductor device also includes a gate field plate connecting the gate electrode and disposed over a portion of the protection layer between the gate electrode and the drain electrode. The gate field plate has an extension portion extending into the protection layer.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: September 21, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chia-Hao Lee, Chang-Xiang Hung, Manoj Kumar, Chih-Cherng Liao
  • Publication number: 20210280693
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a first well region, a second well region, an isolation structure, and a gate structure. The first well region is disposed in the substrate. The second well region is disposed in the substrate. The second well region is adjoining the first well region. The isolation structure is disposed in the first well region. The gate structure is disposed on the substrate. The gate structure includes a first gate portion and a second gate portion. The first gate portion overlaps the first well region and the second well region. There is an opening between the first gate portion and the second gate portion exposing a portion of the isolation structure.
    Type: Application
    Filed: March 4, 2020
    Publication date: September 9, 2021
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Hung LIN, Chia-Hao LEE
  • Publication number: 20210257466
    Abstract: A semiconductor device includes a compound semiconductor layer disposed on a substrate, a protection layer disposed on the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device also includes a plurality of field plates disposed over the protection layer and between the gate electrode and the drain electrode, wherein the plurality of field plates are separated from each other.
    Type: Application
    Filed: May 6, 2021
    Publication date: August 19, 2021
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Hsin-Chih LIN, Chang-Xiang HUNG, Chia-Ching HUANG, Yung-Hao LIN, Chia-Hao LEE
  • Publication number: 20210230130
    Abstract: The present invention relates to a non-fullerene acceptor compound containing benzoselenadiazole, and organic optoelectronic devices comprising the same.
    Type: Application
    Filed: November 27, 2020
    Publication date: July 29, 2021
    Inventors: YU-TANG HSIAO, CHIA-HAO LEE, CHUANG-YI LIAO, CHUN-CHIEH LEE, CHIA-HUA LI, HSIUAN-LING HO, YI-MING CHANG