Patents by Inventor Chia-Hong Jan

Chia-Hong Jan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10707346
    Abstract: A high-voltage transistor structure is provided that includes a self-aligned isolation feature between the gate and drain. Normally, the isolation feature is not self-aligned. The self-aligned isolation process can be integrated into standard CMOS process technology. In one example embodiment, the drain of the transistor structure is positioned one pitch away from the active gate, with an intervening dummy gate structure formed between the drain and active gate structure. The dummy gate structure is sacrificial in nature and can be utilized to create a self-aligned isolation recess, wherein the gate spacer effectively provides a template for etching the isolation recess. This self-aligned isolation forming process eliminates a number of the variation and dimensional constraints attendant non-aligned isolation forming techniques, which in turn allows for smaller footprint and tighter alignment so as to reduce device variation.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Chia-Hong Jan
  • Patent number: 10692888
    Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Jeng-Ya D. Yeh, Curtis Tsai, Joodong Park, Chia-Hong Jan, Gopinath Bhimarasetti
  • Patent number: 10692771
    Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Roman W. Olac-Vaw, Walid M. Hafez, Chia-Hong Jan, Pei-Chi Liu
  • Publication number: 20200194599
    Abstract: Metal-oxide-polysilicon tunable resistors and methods of fabricating metal-oxide-polysilicon tunable resistors are described. In an example, a tunable resistor includes a polysilicon resistor structure disposed above a substrate. A gate oxide layer is disposed on the polysilicon resistor structure. A metal gate layer is disposed on the gate oxide layer.
    Type: Application
    Filed: December 11, 2015
    Publication date: June 18, 2020
    Inventors: Kinyip PHOA, Jui-Yen LIN, Nidhi NIDHI, Chia-Hong JAN
  • Patent number: 10658361
    Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Curtis Tsai, Chia-Hong Jan, Jeng-Ya David Yeh, Joodong Park, Walid M. Hafez
  • Patent number: 10643999
    Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Chia-Hong Jan, Walid M Hafez, Jeng-Ya David Yeh, Hsu-Yu Chang, Neville L Dias, Chanaka D Munasinghe
  • Publication number: 20200105746
    Abstract: A method for fabricating a semiconductor structure includes forming a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is formed over a first of the plurality of semiconductor fins. A second gate structure is formed over a second of the plurality of semiconductor fins. A gate edge isolation structure is formed laterally between and in contact with the first gate structure and the second gate structure, the gate edge isolation structure on the trench isolation region and extending above an uppermost surface of the first gate structure and the second gate structure. A precision resistor is formed on the gate edge isolation structure, wherein the precision resistor and the first gate structure and second gate structure comprise a same material layer.
    Type: Application
    Filed: September 29, 2018
    Publication date: April 2, 2020
    Inventors: Roman OLAC-VAW, Nick LINDERT, Chia-Hong JAN, Walid HAFEZ
  • Publication number: 20200066897
    Abstract: Ultra-scaled fin pitch processes having dual gate dielectrics are described. For example, a semiconductor structure includes first and second semiconductor fins above a substrate. A first gate structure includes a first gate electrode over a top surface and laterally adjacent to sidewalls of the first semiconductor fin, a first gate dielectric layer between the first gate electrode and the first semiconductor fin and along sidewalls of the first gate structure, and a second gate dielectric layer between the first gate electrode and the first gate dielectric layer and along the first gate dielectric layer along the sidewalls of the first gate electrode. A second gate structure includes a second gate electrode over a top surface and laterally adjacent to sidewalls of the second semiconductor fin, and the second gate dielectric layer between the second gate electrode and the second semiconductor fin and along sidewalls of the second gate electrode.
    Type: Application
    Filed: September 30, 2016
    Publication date: February 27, 2020
    Inventors: Walid M. HAFEZ, Roman W. OLAC-VAW, Joodong PARK, Chen-Guan LEE, Chia-Hong JAN, Everett S. CASSIDY-COMFORT
  • Publication number: 20200066907
    Abstract: A transistor device including a transistor including a body disposed on a substrate, a gate stack contacting at least two adjacent sides of the body and a source and a drain on opposing sides of the gate stack and a channel defined in the body between the source and the drain, wherein a conductivity of the channel is similar to a conductivity of the source and the drain. An input/output (IO) circuit including a driver circuit coupled to the logic circuit, the driver circuit including at least one transistor device is described. A method including forming a channel of a transistor device on a substrate including an electrical conductivity; forming a source and a drain on opposite sides of the channel, wherein the source and the drain include the same electrical conductivity as the channel; and forming a gate stack on the channel.
    Type: Application
    Filed: September 30, 2016
    Publication date: February 27, 2020
    Inventors: Chia-Hong JAN, Walid M. HAFEZ, Hsu-Yu CHANG, Neville L. DIAS, Rahul RAMASWAMY, Roman W. OLAC-VAW, Chen-Guan LEE
  • Publication number: 20200066712
    Abstract: Metal resistors and self-aligned gate edge (SAGE) architectures having metal resistors are described. In an example, a semiconductor structure includes a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is over a first of the plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A gate edge isolation structure is laterally between and in contact with the first gate structure and the second gate structure. The gate edge isolation structure is on the trench isolation region and extends above an uppermost surface of the first gate structure and the second gate structure. A metal layer is on the gate edge isolation structure and is electrically isolated from the first gate structure and the second gate structure.
    Type: Application
    Filed: September 29, 2016
    Publication date: February 27, 2020
    Inventors: Walid M. HAFEZ, Roman W. OLAC-VAW, Joodong PARK, Chen-Guan LEE, Chia-Hong JAN
  • Patent number: 10559688
    Abstract: Techniques are disclosed for forming a transistor with enhanced thermal performance. The enhanced thermal performance can be derived from the inclusion of thermal boost material adjacent to the transistor, where the material can be selected based on the transistor type being formed. In the case of PMOS devices, the adjacent thermal boost material may have a high positive linear coefficient of thermal expansion (CTE) (e.g., greater than 5 ppm/° C. at around 20° C.) and thus expand as operating temperatures increase, thereby inducing compressive strain on the channel region of an adjacent transistor and increasing carrier (e.g., hole) mobility. In the case of NMOS devices, the adjacent thermal boost material may have a negative linear CTE (e.g., less than 0 ppm/° C. at around 20° C.) and thus contract as operating temperatures increase, thereby inducing tensile strain on the channel region of an adjacent transistor and increasing carrier (e.g., electron) mobility.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: February 11, 2020
    Assignee: Intel Corporation
    Inventors: Chen-Guan Lee, Walid M. Hafez, Joodong Park, Chia-Hong Jan, Hsu-Yu Chang
  • Publication number: 20200043914
    Abstract: Techniques are disclosed for forming semiconductor structures including resistors between gates on self-aligned gate edge architecture. A semiconductor structure includes a first semiconductor fin extending in a first direction, and a second semiconductor fin adjacent to the first semiconductor fin, extending in the first direction. A first gate structure is disposed proximal to a first end of the first semiconductor fin and over the first semiconductor fin in a second direction, orthogonal to the first direction, and a second gate structure is disposed proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction. A first structure comprising isolation material is centered between the first and second semiconductor fins. A second structure comprising resistive material is disposed in the first structure, the second structure extending at least between the first gate structure and the second gate structure.
    Type: Application
    Filed: March 31, 2017
    Publication date: February 6, 2020
    Applicant: INTEL CORPORATION
    Inventors: ROMAN W. OLAC-VAW, WALID M. HAFEZ, CHIA-HONG JAN, HSU-YU CHANG, NEVILLE L. DIAS, RAHUL RAMASWAMY, NIDHI NIDHI, CHEN-GUAN LEE
  • Patent number: 10535747
    Abstract: Techniques are disclosed for forming a transistor with one or more additional gate spacers. The additional spacers may be formed between the gate and original gate spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion and an upper portion. In some such cases, the lower portion of the gate may be narrower in width between the original gate spacers than the upper portion of the gate, which may be as a result of the additional spacers being located between the lower portion of the gate and the original gate spacers. In some such cases, the gate may approximate a “T” shape or various derivatives of that shape such as -shape or -shape, for example.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: January 14, 2020
    Assignee: INTEL CORPORATION
    Inventors: En-Shao Liu, Joodong Park, Chen-Guan Lee, Chia-Hong Jan
  • Publication number: 20200006509
    Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, C-shape, -shape, ?-shape, L-shape, or ?-shape, for example.
    Type: Application
    Filed: September 13, 2019
    Publication date: January 2, 2020
    Applicant: INTEL CORPORATION
    Inventors: EN-SHAO LIU, JOODONG PARK, CHEN-GUAN LEE, JUI-YEN LIN, CHIA-HONG Jan
  • Publication number: 20190356032
    Abstract: Embodiments of the invention include an electromagnetic waveguide and methods of forming the electromagnetic waveguide. In an embodiment the electromagnetic waveguide includes a first spacer and a second spacer. In an embodiment, the first and second spacer each have a reentrant profile. The electromagnetic waveguide may also include a conductive body formed between in the first and second spacer, and a void formed within the conductive body. In an additional embodiment, the electromagnetic waveguide may include a first spacer and a second spacer. Additionally, the electromagnetic waveguide may include a first portion of a conductive body formed along sidewalls of the first and second spacer and a second portion of the conductive body formed between an upper portion of the first portion of the conductive body. In an embodiment, the first portion of the conductive body and the second portion of the conductive body define a void through the electromagnetic waveguide.
    Type: Application
    Filed: December 30, 2016
    Publication date: November 21, 2019
    Inventors: Rahul RAMASWAMY, Chia-Hong JAN, Walid HAFEZ, Neville DIAS, Hsu-Yu CHANG, Roman OLAC-VAW, Chen-Guan LEE
  • Publication number: 20190305112
    Abstract: Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Inventors: Sairam SUBRAMANIAN, Walid M. HAFEZ, Sridhar GOVINDARAJU, Mark LIU, Szuya S. LIAO, Chia-Hong JAN, Nick LINDERT, Christopher KENYON
  • Publication number: 20190304840
    Abstract: An apparatus comprising at least one transistor in a first area of a substrate and at least one transistor in a second area, a work function material on a channel region of each of the at least one transistor, wherein an amount of work function material in the first area is different than an amount of work function material in the second area. A method comprising depositing a work function material and a masking material on at least one transistor body in a first area and at least one in a second area; removing less than an entire portion of the masking material so that the portion of the work function material that is exposed in the first area is different than that exposed in the second area; removing the exposed work function material; and forming a gate electrode on each of the at least one transistor bodies.
    Type: Application
    Filed: September 30, 2016
    Publication date: October 3, 2019
    Inventors: Chen-Guan LEE, Everett S. CASSIDY-COMFORT, Joodong PARK, Walid M. HAFEZ, Chia-Hong JAN, Rahul RAMASWAMY, Neville L. DIAS, Hsu-Yu CHANG
  • Publication number: 20190304971
    Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Inventors: Walid M. HAFEZ, Sridhar GOVINDARAJU, Mark LIU, Szuya S. LIAO, Chia-Hong JAN, Nick LINDERT, Christopher KENYON, Sairam SUBRAMANIAN
  • Publication number: 20190305111
    Abstract: Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Inventors: Sairam SUBRAMANIAN, Christopher KENYON, Sridhar GOVINDARAJU, Chia-Hong JAN, Mark LIU, Szuya S. LIAO, Walid M. HAFEZ
  • Patent number: 10431661
    Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, -shape, -shape, ?-shape, L-shape, or ?-shape, for example.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: October 1, 2019
    Assignee: INTEL CORPORATION
    Inventors: En-Shao Liu, Joodong Park, Chen-Guan Lee, Jui-Yen Lin, Chia-Hong Jan