Patents by Inventor Chia-Hsuan Tsai
Chia-Hsuan Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12162749Abstract: A semiconductor device and method of manufacturing the device that includes a growth die and a dummy die. The method includes patterning, on an integrated circuit wafer, at one least growth die, and patterning at least one dummy die that is positioned on at least a portion of a circumference of the integrated circuit wafer. The patterned growth and dummy dies are etched on the wafer. A bond wave is initiated at a starting point on the integrated circuit wafer. The starting point is positioned on an edge of the integrated circuit wafer opposite the portion on which the at least one dummy die is patterned. Upon application of pressure at the starting point, a uniform bond wave propagates across the wafers, bonding the two wafers together.Type: GrantFiled: August 9, 2023Date of Patent: December 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kang-Yi Lien, I-Hsuan Chiu, Yi-Chieh Huang, Chia-Ming Hung, Kuan-Chi Tsai, Hsiang-Fu Chen
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Patent number: 12155328Abstract: A multi-axis servo control system includes a plurality of motors and a plurality of drive control apparatuses. The drive control apparatuses are connected to each other through an external field bus. Each drive control apparatus includes a control unit and a plurality of drive units. The drive units are connected to the control unit in series by a plurality of local buses to form a series-connected communication loop of sequentially transmitting data. Each drive unit controls at least one of the motors. The control unit receives multi-axis position commands through the external field bus, and the drive units correspondingly receive multi-axis commands through the local buses so as to control the motors in a decentralization manner.Type: GrantFiled: March 21, 2022Date of Patent: November 26, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Chien-Da Chen, I-Hsuan Tsai, Chia-Hua Lee, Ching-Wei Huang
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Publication number: 20240363464Abstract: A package structure is provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The through via extends through the encapsulant and the first redistribution line structure and connecting the second RDL structure. The through via is laterally separated from the redistribution layer by the dielectric layer therebetween.Type: ApplicationFiled: July 9, 2024Publication date: October 31, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo
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Publication number: 20240334231Abstract: Examples pertaining to measurement resource and report configuration for a communication apparatus supporting device collaboration in mobile communications are described. A user equipment (UE) receives a first report configuration associated with at least a first measurement resource allocated in a first frequency band from a network node. The UE determines information regarding a second measurement resource allocated in a second frequency band which is different from the first frequency band. The UE receives a first radio frequency (RF) signal carrying one or more reference signals on the first measurement resource and receives a second RF signal carrying identical one or more reference signals on the second measurement resource.Type: ApplicationFiled: March 5, 2024Publication date: October 3, 2024Inventors: Lung-Sheng Tsai, Chia-Hao Yu, Cheng-Rung Tsai, Chi-Hsuan Hsieh
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Publication number: 20240331862Abstract: The present invention provides a data analytic scheme for screening biomarkers for differential diagnosis of the status of Parkinson's disease, Parkinson's disease with mild cognitive impairment, Parkinson's disease dementia, Alzheimer's disease, and/or multiple system atrophy, the methodology implementing the same and the results of the screening thereof. Biomedical Oriented Logistic Dantzig Selector (BOLD Selector) was developed to identify candidate microRNAs and extracellular vesicle proteins effective at discerning between any two of the above mentioned disease categories from profiling results. The prediction models are finalized by establishing logistic regression formula for each pair of patient group differentiation.Type: ApplicationFiled: March 29, 2024Publication date: October 3, 2024Inventors: Shau-Ping LIN, Ruey-Meei WU, Frederick Kin Hing Phoa, Ming-Che KUO, Yi-Tzang TSAI, Jing-Wen HUANG, Yan-Han LIN, Hsiang-Hsuan LIN WANG, Chia-Lang HSU, Ya-Fang HSU, Pin-Jui KUNG
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Patent number: 12105006Abstract: A gas detection system for gynecological disease detection and a detection method using the same are provided. The gas detection system is configured to detect an analyte from a female vagina and includes a main body, a sleeve, a detector, a pump, and a controller. The main body includes a body portion and a head portion having an intake channel. The body portion includes a detection chamber and an exhaust channel. The detector includes at least one sensor configured to detect at least one target of the analyte and produce at least one detection signal. The pump is communicated with the detection chamber and the exhaust channel. The controller includes a processing unit and a first communication unit. The processing unit receives the at least one detection signal and controls the first communication unit to send the at least one detection signal.Type: GrantFiled: April 20, 2021Date of Patent: October 1, 2024Assignee: AINOS, INC.Inventors: Chia-Nan Liao, Chia-Pin Huang, Tzu-Ting Weng, Yu-Hsuan Liao, Chun-Hsien Tsai, Ting-Chuan Lee, Chun-Jung Tsai
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Publication number: 20240297163Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.Type: ApplicationFiled: May 12, 2024Publication date: September 5, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai
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Patent number: 12068212Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, a conductive terminal, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The conductive terminal is connected to the redistribution layer. The through via extends through the encapsulant and the redistribution layer to contact the conductive terminal and the second RDL structure.Type: GrantFiled: April 11, 2022Date of Patent: August 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo
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Publication number: 20240275274Abstract: A Totem-pole power factor corrector receives an input power source and convert the input power source into an output power source. The Totem-pole power factor corrector includes an input inductor, a fast-switching switch leg, a slow-switching switch leg, a resonant tank, and an output capacitor. The fast-switching switch leg includes a fast-switching upper switch and a fast-switching lower switch, and the fast-switching upper switch and the fast-switching lower switch are commonly coupled at a first middle node. The slow-switching switch leg is coupled in parallel to the fast-switching switch leg, and the slow-switching switch leg includes a slow-switching upper and a slow-switching lower switch. The resonant tank includes a resonant inductor and at least one resonant capacitor. A first end of the resonant inductor is coupled to the first middle node, and a second end of the resonant inductor is coupled to the at least one capacitor.Type: ApplicationFiled: June 8, 2023Publication date: August 15, 2024Inventors: Feng-Hsuan TUNG, Terng-Wei TSAI, Chia-Hsiong HUANG, Yu-Jen LIN
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Publication number: 20240275276Abstract: A flying capacitor converter with zero-zero switching includes an input inductor, a fast-switching switch leg, a slow-switching switch leg, at least one flying capacitor, a resonant tank, and an output capacitor. The fast-switching switch leg included an upper leg having a plurality of upper switches and a lower leg having a plurality of lower switches. The slow-switching switch leg includes a slow-switching upper switch and a slow-switching lower switch, and the slow-switching upper switch and the slow-switching lower switch are coupled at a second middle node. The at least one flying capacitor is correspondingly coupled between the upper node and the lower node. The resonant tank includes a resonant inductor and a resonant capacitor, and the resonant inductor and the resonant capacitor are coupled in series between the first middle node and the second middle node.Type: ApplicationFiled: June 8, 2023Publication date: August 15, 2024Inventors: Feng-Hsuan TUNG, Terng-Wei TSAI, Chia-Hsiong HUANG, Yu-Jen LIN
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Patent number: D808638Type: GrantFiled: July 14, 2015Date of Patent: January 30, 2018Assignee: Tricella Inc.Inventors: Daniel M. Weng, Chia-Hsuan Tsai
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Patent number: D849395Type: GrantFiled: December 18, 2017Date of Patent: May 28, 2019Assignee: Tricella Inc.Inventors: Daniel M. Weng, Chia-Hsuan Tsai