Patents by Inventor Chia-Hung Lai

Chia-Hung Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240089188
    Abstract: A monitoring system and a monitoring method of network latency are provided. The monitoring method includes: making a server communicatively connect to a first host and a second host, wherein the first host provides a first virtual machine operating a first application and the second host provides a second virtual machine operating a second application; and calculating, by the server, time latency information associated with a communication between the first application and the second application according to data obtained from the first host and the second host, and displaying the time latency information through a visual interface, wherein the time latency information includes a total latency of the communication between the first application and the second application.
    Type: Application
    Filed: November 2, 2022
    Publication date: March 14, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Te-Yen Liu, Chia Hung Lai
  • Patent number: 11094579
    Abstract: A method of forming a semiconductor structure includes depositing a mask layer over a substrate. The method includes etching the substrate to define a first opening. The method includes depositing a sacrificial material in the first opening. The method includes depositing a dielectric liner along sidewalls of the first opening, wherein a bottom surface of the dielectric liner contacts the sacrificial material. The method includes removing the sacrificial material. The method includes etching the substrate to enlarge the first opening to define a second opening. The second opening includes a first portion extending a first depth from the dielectric material in a first direction perpendicular to a top surface of the substrate, and a second portion extending in a second direction, parallel to the top surface of the substrate. The method includes removing the dielectric liner. The method includes filling the second opening with a dielectric material.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Bin Huang, Chien-Mao Chen, Yu-Hsuan Kuo, Shih-Kai Fan, Chia-Hung Lai, Kang-Min Kuo
  • Patent number: 10871720
    Abstract: In embodiments of the present disclosure, a vibrator is used to generate a vibration wave with a variable frequency that can agitate and facilitate the circulation of the processing fluids, thereby enhancing the uniformity and efficiency of the resulting semiconductor device features, the vibrator may be a piezoelectric vibrator or other similar vibrators. In some embodiments, the vibration of the processing fluids can facilitate the processing fluids in circulating in and out of narrow channels or features, or the vibration of the processing fluids can facilitate the bubbling out of the microbubbles entrapped in the processing liquid or entrapped between the surface of the semiconductor wafer and the processing liquid. In another embodiment, the vibrations generated by the vibrator have vibration waves with a variable frequency to avoid resonance that may damage the semiconductor wafer and the features thereon.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Astha Sharma, Chia-Hung Lai, Hsin-Kuo Chang, Jaw-Lih Shih, Hong-Hsing Chou
  • Publication number: 20200286774
    Abstract: A method of forming a semiconductor structure includes depositing a mask layer over a substrate. The method includes etching the substrate to define a first opening. The method includes depositing a sacrificial material in the first opening. The method includes depositing a dielectric liner along sidewalls of the first opening, wherein a bottom surface of the dielectric liner contacts the sacrificial material. The method includes removing the sacrificial material. The method includes etching the substrate to enlarge the first opening to define a second opening. The second opening includes a first portion extending a first depth from the dielectric material in a first direction perpendicular to a top surface of the substrate, and a second portion extending in a second direction, parallel to the top surface of the substrate. The method includes removing the dielectric liner. The method includes filling the second opening with a dielectric material.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: Yen-Bin HUANG, Chien-Mao CHEN, Yu-Hsuan KUO, Shih-Kai FAN, Chia-Hung LAI, Kang-Min KUO
  • Patent number: 10699938
    Abstract: A semiconductor structure includes a shallow trench isolation (STI) structure. The semiconductor structure includes a substrate having a first surface. A STI structure extends from the first surface into the substrate. The STI structure includes a first portion and a second portion. The first portion extends from the first surface into the substrate, and has an intersection with the first surface. The second portion extends away from the first portion, and has a tip at a distance away from the intersection in a direction parallel to the first surface. The first portion and the second portion are filled with a dielectric material.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Bin Huang, Chien-Mao Chen, Yu-Hsuan Kuo, Shih-Kai Fan, Chia-Hung Lai, Kang-Min Kuo
  • Publication number: 20160096155
    Abstract: In embodiments of the present disclosure, a vibrator is used to generate a vibration wave with a variable frequency that can agitate and facilitate the circulation of the processing fluids, thereby enhancing the uniformity and efficiency of the resulting semiconductor device features, the vibrator may be a piezoelectric vibrator or other similar vibrators. In some embodiments, the vibration of the processing fluids can facilitate the processing fluids in circulating in and out of narrow channels or features, or the vibration of the processing fluids can facilitate the bubbling out of the microbubbles entrapped in the processing liquid or entrapped between the surface of the semiconductor wafer and the processing liquid. In another embodiment, the vibrations generated by the vibrator have vibration waves with a variable frequency to avoid resonance that may damage the semiconductor wafer and the features thereon.
    Type: Application
    Filed: October 2, 2014
    Publication date: April 7, 2016
    Inventors: Astha SHARMA, Chia-Hung LAI, Hsin-Kuo CHANG, Jaw-Lih SHIH, Hong-Hsing CHOU
  • Patent number: 9269257
    Abstract: The method and system for reminding readers of fatigue in reading while using electronic devices are revealed. First use a reading speed calculation module to detect user's reading speed within a period of time when the user is using an electronic with a display to read. The reading speed is related to pages being turned or the amount of words being read. Then a fatigue-in-reading reminder module is activated by the reading speed calculation module when the user's reading speed falls within a specific range so as to remind the user by pop-up windows, sounds, flash light or vibration at the proper time and provide the user certain corresponding measures he/she should take. Thereby there is no need to use additional equipment for preventing users from becoming more fatigue and healthy vision is accomplished at lower cost with higher efficiency.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: February 23, 2016
    Assignee: National Cheng Kung University
    Inventors: Yueh-Min Huang, Chia-Ju Liu, Chia-Hung Lai, Yen-Ning Su, Chia-Cheng Hsu, Yu-Cheng Chien, Tsung-Ho Liang, Tzu-Chien Liu, Fu-Yun Yu, Yu-Lin Jeng
  • Patent number: 9066566
    Abstract: A transparent shell structure for luggage and the like includes an outer shell, a decorative plate, a lining, and a plurality of corner protectors. The outer shell has an inner space with a frame. One side of the decorative plate is a patterned surface. Each of the four corners of the decorative plate has a notch, so that the four sides thereof are bent inside the inner space. The decorative plate is restricted within the outer shell. The lining is attached to the decorative plate and disposed in the inner space of the outer shell with the decorative plate, connecting to the frame by the sides. The corner protectors are connected to the four corners of the outer shell.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: June 30, 2015
    Inventor: Chia-Hung Lai
  • Publication number: 20150021700
    Abstract: A semiconductor structure includes a shallow trench isolation (STI) structure. The semiconductor structure includes a substrate having a first surface. A STI structure extends from the first surface into the substrate. The STI structure includes a first portion and a second portion. The first portion extends from the first surface into the substrate, and has an intersection with the first surface. The second portion extends away from the first portion, and has a tip at a distance away from the intersection in a direction parallel to the first surface. The first portion and the second portion are filled with a dielectric material.
    Type: Application
    Filed: July 18, 2013
    Publication date: January 22, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Bin HUANG, Chien-Mao CHEN, Yu-Hsuan KUO, Shih-Kai FAN, Chia-Hung LAI, Kang-Min KUO
  • Publication number: 20140333435
    Abstract: The method and system for reminding readers of fatigue in reading while using electronic devices are revealed. First use a reading speed calculation module to detect user's reading speed within a period of time when the user is using an electronic with a display to read. The reading speed is related to pages being turned or the amount of words being read. Then a fatigue-in-reading reminder module is activated by the reading speed calculation module when the user's reading speed falls within a specific range so as to remind the user by pop-up windows, sounds, flash light or vibration at the proper time and provide the user certain corresponding measures he/she should take. Thereby there is no need to use additional equipment for preventing users from becoming more fatigue and healthy vision is accomplished at lower cost with higher efficiency.
    Type: Application
    Filed: July 19, 2013
    Publication date: November 13, 2014
    Applicant: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: YUEH-MIN HUANG, CHIA-JU LIU, CHIA-HUNG LAI, YEN-NING SU, CHIA-CHENG HSU, YU-CHENG CHIEN, TSUNG-HO LIANG, TZU-CHIEN LIU, FU-YUN YU, YU-LIN JENG
  • Publication number: 20140224608
    Abstract: A suitcase with a protective cover includes a main body having two semi-sphere cases, two adaptors respectively mounted fixedly around the corresponding sides of the two semi-sphere cases, a close space formed by the two semi-sphere cases, the adaptors having at least one first adapting portion mounted along the locations around which each of the adaptors is mounted, two cover bodies, each of the cover bodies has an opening, a concave portion recessed from the opening, a positioning rim mounted around the side of the opening, the concave portion having depth being capable of having the cover bodies cover the semi-sphere cases, at least one second adapting portion mounted along the locations around which each of the positioning rims is mounted, and each cover body fixed on each corresponding semi-spheres case via the connection of the at least one first adapting portion and the second adapting portion.
    Type: Application
    Filed: February 5, 2014
    Publication date: August 14, 2014
    Inventors: CHIA-HUNG LAI, JAPHIE HSU
  • Publication number: 20140008164
    Abstract: A transparent shell structure for luggage and the like includes an outer shell, a decorative plate, a lining, and a plurality of corner protectors. The outer shell has an inner space with a frame. One side of the decorative plate is a patterned surface. Each of the four corners of the decorative plate has a notch, so that the four sides thereof are bent inside the inner space. The decorative plate is restricted within the outer shell. The lining is attached to the decorative plate and disposed in the inner space of the outer shell with the decorative plate, connecting to the frame by the sides. The corner protectors are connected to the four corners of the outer shell.
    Type: Application
    Filed: January 15, 2013
    Publication date: January 9, 2014
    Inventors: Chia-Hung LAI, Meng-Chun LAI CHU, Chen Yueh HSU
  • Patent number: 8461857
    Abstract: The present invention relates to a distance adjustment system and a solar wafer inspection machine provided with the system. The inspection machine has a conveyer for carrying a solar wafer, an optical inspection system for inspecting the surface and color appearance of the wafer and an illumination inspection system. A holder is provided in the inspection position where the wafer is clamped along its width direction to prevent the wafer from offset. During the opto-electrical inspection, probes are brought into contact with conductive buses of the wafer and light is applied to the wafer to allow the probing of electric energy thus generated. An adjusting device is employed to adjust the clamping gap of the holder and the distance of the probes in accordance with the size of the solar wafer. The data are collected and transmitted to a sorting system for sorting the wafer.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: June 11, 2013
    Assignee: Chroma Ate Inc.
    Inventor: Chia-Hung Lai
  • Publication number: 20120013897
    Abstract: The present invention relates to a distance adjustment system and a solar wafer inspection machine provided with the system. The inspection machine has a conveyer for carrying a solar wafer, an optical inspection system for inspecting the surface and color appearance of the wafer and an illumination inspection system. A holder is provided in the inspection position where the wafer is clamped along its width direction to prevent the wafer from offset. During the opto-electrical inspection, probes are brought into contact with conductive buses of the wafer and light is applied to the wafer to allow the probing of electric energy thus generated. An adjusting device is employed to adjust the clamping gap of the holder and the distance of the probes in accordance with the size of the solar wafer. The data are collected and transmitted to a sorting system for sorting the wafer.
    Type: Application
    Filed: February 18, 2011
    Publication date: January 19, 2012
    Applicant: CHROMA ATE INC.
    Inventor: Chia-Hung Lai
  • Patent number: 7160811
    Abstract: A method for fabricating a microelectronic fabrication employs an undoped silicate glass layer as an etch stop layer when etching a doped silicate glass layer with an anhydrous hydrofluoric acid etchant. The method is particularly useful for forming a patterned salicide blocking dielectric layer when fabricating a complementary metal oxide semiconductor device.
    Type: Grant
    Filed: October 22, 2002
    Date of Patent: January 9, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ming Chen, Huan-Chi Tseng, Yu-Hua Lee, Dian-Hau Chen, Chia-Hung Lai, Kang-Min Kuo
  • Publication number: 20060194426
    Abstract: A method for manufacturing a dual damascene structure, which forms a trench first, is described. The manufacturing method has following steps. First, a substrate with a plurality of semiconductor devices is provided. A first metal layer, a first etching stop layer, a dielectric layer, and a second etching stop layer are subsequently formed thereon. A trench is formed in the dielectric layer at a predetermined depth thereafter, and a sacrificial layer is filled therein and is next planarized. Then a photoresist layer is formed thereon for etching a via. Afterward the photoresist layer and the sacrificial layer are both removed. Following that, the first etching stop layer is etched through to expose the first metal layer. Finally, the via and the trench are filled with a second metal layer.
    Type: Application
    Filed: April 11, 2006
    Publication date: August 31, 2006
    Inventors: Chin-Tien Yang, Juan-Jann Jou, Yu-Hua Lee, Chia-Hung Lai
  • Patent number: 7056821
    Abstract: A method for manufacturing a dual damascene structure, which forms a trench first, is described. The manufacturing method has following steps. First, a substrate with a plurality of semiconductor devices is provided. A first metal layer, a first etching stop layer, a dielectric layer, and a second etching stop layer are subsequently formed thereon. A trench is formed in the dielectric layer at a predetermined depth thereafter, and a sacrificial layer is filled therein and is next planarized. Then a photoresist layer is formed thereon for etching a via. Afterward the photoresist layer and the sacrificial layer are both removed. Following that, the first etching stop layer is etched through to expose the first metal layer. Finally, the via and the trench are filled with a second metal layer.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: June 6, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Tien Yang, Juan-Jann Jou, Yu-Hua Lee, Chia-Hung Lai
  • Patent number: 7015129
    Abstract: A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: March 21, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hung Lai, Jiunn-Jyi Lin, Tzong-Sheng Chang, Min Cao, Huan-Chi Tseng, Yu-Hua Lee, Chin-Tien Yang
  • Publication number: 20060040498
    Abstract: A method for manufacturing a dual damascene structure, which forms a trench first, is described. The manufacturing method has following steps. First, a substrate with a plurality of semiconductor devices is provided. A first metal layer, a first etching stop layer, a dielectric layer, and a second etching stop layer are subsequently formed thereon. A trench is formed in the dielectric layer at a predetermined depth thereafter, and a sacrificial layer is filled therein and is next planarized. Then a photoresist layer is formed thereon for etching a via. Afterward the photoresist layer and the sacrificial layer are both removed. Following that, the first etching stop layer is etched through to expose the first metal layer. Finally, the via and the trench are filled with a second metal layer.
    Type: Application
    Filed: August 17, 2004
    Publication date: February 23, 2006
    Inventors: Chin-Tien Yang, Juan-Jann Jou, Yu-Hua Lee, Chia-Hung Lai
  • Publication number: 20050173799
    Abstract: A method of fabricating an interconnect structure, including providing a semiconductor substrate having a first conductive layer thereon, and forming a dielectric layer overlying the semiconductor substrate and the first conductive layer. An opening is formed in the dielectric layer extending to the first conductive layer. A portion of the first conductive layer is removed through the opening to form a recess having a substantially curvilinear profile. The opening and the recess are filled with a second conductive layer.
    Type: Application
    Filed: February 5, 2004
    Publication date: August 11, 2005
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Juan-Jann Jou, Yu-Hua Lee, Chin-Tien Yang, Chia-Hung Lai, Connie Hsu, Mu-Yi Lin, Min Cao, Chia-Yu Ku, Yuh-Da Fan