Patents by Inventor Chia-Hung Liu

Chia-Hung Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10510631
    Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, a redistribution layer (RDL) structure, a through integrated fan-out via (TIV) and a first connector. The RDL structure is connected to the die and includes a plurality of RDLs. The TIV is aside the die and penetrates through the RDL structure. The first connector is in electrical contact with the TIV and electrically connected to the die. The TIV is in electrical contact with the RDLs of the RDL structure.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo
  • Patent number: 10510891
    Abstract: Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Chun-Hung Wu, Chia-Cheng Chen, Liang-Yin Chen, Huicheng Chang, Ying-Lang Wang
  • Publication number: 20190378928
    Abstract: Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.
    Type: Application
    Filed: July 8, 2019
    Publication date: December 12, 2019
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Chun-Hung Wu, Chia-Cheng Chen, Liang-Yin Chen, Huicheng Chang, Ying-Lang Wang
  • Publication number: 20190369499
    Abstract: Embodiments herein beneficially enable simultaneous processing of a plurality of substrates in a digital direct write lithography processing system. In one embodiment a method of processing a plurality of substrate includes positioning a plurality of substrates on a substrate carrier of a processing system, positioning the substrate carrier under the plurality of optical modules, independently leveling each of the plurality of substrates, determining offset information for each of the plurality of substrates, generating patterning instructions based on the offset information for each of the plurality of substrates, and patterning each of the plurality of substrates using the plurality of optical modules. The processing system comprises a base, a motion stage disposed on the base, the substrate carrier disposed on the motion stage, a bridge disposed above a surface of the base and separated therefrom, and a plurality of optical modules disposed on the bridge.
    Type: Application
    Filed: March 19, 2019
    Publication date: December 5, 2019
    Inventors: Chien-Hua LAI, Chia-Hung KAO, Hsiu-Jen WANG, Shih-Hao KUO, Yi-Sheng LIU, Shih-Hsien LEE, Ching-Chang CHEN, Tsu-Hui YANG
  • Patent number: 10468700
    Abstract: A membrane-electrode assembly for water electrolysis including a proton-exchange membrane, a first catalyst layer, a second catalyst layer, a first gas diffusion layer, a second gas diffusion layer and a first sensor chip. The proton-exchange membrane is disposed between an inner side of the first catalyst layer and an inner side of the second catalyst layer. The first gas diffusion layer is disposed on an outer side of the first catalyst layer. The second gas diffusion layer is disposed on an outer side of the second catalyst layer. The first sensor chip is sandwiched between the first catalyst layer and the first gas diffusion layer to sense an environmental change where water electrolysis takes place.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: November 5, 2019
    Assignees: YUAN ZE UNIVERSITY, HOMYTECH CO., LTD.
    Inventors: Chi-Yuan Lee, Chia-Hung Chen, Guo-Bin Jung, Yu-Chun Chiang, Chin-Lung Hsieh, Yun-Min Liu
  • Patent number: 10470323
    Abstract: A hinge structure includes a first base, a second base, a first linking rod, a second linking rod, and a torque assembly. The first linking rod has a first pivot part, a first sliding part, and a second pivot part. The first pivot part is pivoted to the first base, and the first sliding part is slidably connected to the second base. The second linking rod has a second sliding part, a shaft part, a third pivot part, and a fourth pivot part. The second sliding part is slidably connected to the first base. The third pivot part is pivoted to the second base. The second pivot part is pivoted to the fourth pivot part. The torque assembly has a sleeve part sleeved on the shaft part and a connection part connected to the second base. The sleeve part generates torque during rotation with respect to the shaft part.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: November 5, 2019
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Hsien-Hung Cheng, You-Yu Chen, Chia-Wei Chou, Po-Yi Chang, Cheng-Yo Hsiao, Wei-Ting Liu
  • Publication number: 20190335152
    Abstract: A method for configuring image-recording settings includes receiving an image source, determining whether the image source is the high dynamic range (HDR) image. If a HDR image source is received, a step is performed for determining whether a recording device supports recording an image with a HDR format, and a step is performed for adding a HDR recording option if the recording device supports recording the image with the HDR format.
    Type: Application
    Filed: April 2, 2019
    Publication date: October 31, 2019
    Inventors: Hsiang-Yi MA, Pin-Feng CHIU, Nian-Ying TSAI, Po-Yang YAO, Chia-Hung LIU
  • Patent number: 10459341
    Abstract: Embodiments of the present disclosure generally provide a digital lithography system that can process both large area substrates as well as semiconductor device substrates, such as wafers. Both the large area substrates and the semiconductor device substrates can be processed in the same system simultaneously. Additionally, the system can accommodate different levels of exposure for forming the features over the substrates. For example, the system can accommodate very precise feature patterning as well as less precise feature patterning. The different exposures can occur in the same chamber simultaneously. Thus, the system is capable of processing both semiconductor device substrates and large area substrates simultaneously while also accommodating very precise feature patterning simultaneous with less precise feature patterning.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: October 29, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chien-Hua Lai, Ching-Chang Chen, Shih-Hao Kuo, Tsu-Hui Yang, Hsiu-Jen Wang, Yi-Sheng Liu, Chia-Hung Kao
  • Publication number: 20190304717
    Abstract: A key switch includes a base, a key cap, a supporting mechanism, a link bar and a buffer member. The key cap is disposed above the base. The supporting mechanism is connected to the key cap and the base to allow the key cap to move relative to the base upwardly and downwardly. The link bar includes a lower linking end. The buffer member and the base are two independent components. The buffer member is disposed on the base and made of material softer than material of the base. A restraining structure is formed on the buffer member. The lower linking end movably passes through the restraining structure. When the key cap moves relative to the base upwardly and downwardly, the lower linking end is driven to move within the restraining structure correspondingly, so as to reduce noise during movement of the lower linking end relative to the base.
    Type: Application
    Filed: June 16, 2019
    Publication date: October 3, 2019
    Inventors: Pen-Hui Liao, Chin-Hung Lin, Yen-Hsiao Lin, Hsin-Hung Liu, Chia-Fu Cheng
  • Publication number: 20190304864
    Abstract: A package structure including a semiconductor die, an insulating encapsulant, and a redistribution layer is provided. The semiconductor die includes a semiconductor substrate, a plurality of metallization layers disposed on the semiconductor substrate, and a passivation layer disposed on the plurality of metallization layers. The passivation layer has a first opening that partially expose a topmost layer of the plurality of metallization layers. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer includes at least a first dielectric layer and a first conductive layer stacked on the first dielectric layer. The first dielectric layer has a second opening that overlaps with the first opening, and a width ratio of the second opening to the first opening is in a range of 2.3:1 to 12:1. The first conductive layer is electrically connected to the topmost layer of the plurality of metallization layers through the first and second openings.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Ting Kuo, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Chih-Hsuan Tai, Ying-Cheng Tseng
  • Patent number: 10429318
    Abstract: A detection system for a multilayer film is provided. The detection system for a multilayer film includes a light source device, a first image capture device, a second image capture device and an image processing device. The light source device projects a pair of parallel incident light to a transparent multilayer film obliquely. The pair of parallel incident light is projected onto the transparent multilayer film for producing and enabling a forward scattered light and a back scattered light to be projected therefrom. The first image capture device captures the back scattered light to produce a first image. The second image capture device captures the forward scattered light to produce a second image. The image processing device is coupled to the first image capture device and the second image capture device. The image processing device is used to compares and detect the differences between the second image and the first image.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: October 1, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ding-Kun Liu, Chia-Hung Cho
  • Patent number: 10431402
    Abstract: A button switch connected to a cap and includes a base having a pillar, a flexible acoustic member having fixing and flexible rods, a sleeve, an upward-force-applying member abutting against the sleeve and the base, a resilient arm, and a cover disposed on the base. The sleeve rotatably jackets the pillar, passes through the cover to be connected to the cap, and has first and second convex portions, first and second concave portions, and a protruding edge located between the second convex portion and the second concave portion. The resilient arm selectively abuts against a first or second position on the first convex portion. When the resilient arm abuts against the first position and the protruding edge is located above the flexible rod, the flexible rod crosses the protruding edge and then collides with the cover to make a sound when the sleeve receives an external force to move downward.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: October 1, 2019
    Assignee: DARFON ELECTRONICS CORP.
    Inventors: Yu-Chun Hsieh, Chia-Hung Liu, Yung-Chih Wang, Chen Yang
  • Publication number: 20190288068
    Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.
    Type: Application
    Filed: June 6, 2019
    Publication date: September 19, 2019
    Inventors: Su-Hao Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Kuo-Ju Chen, Chun-Hung Wu, Chang-Maio Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
  • Patent number: 10416031
    Abstract: A pressure sensing mat may include: a first substrate; a second substrate disposed opposite to the first substrate; a first electrode layer disposed on a side of the first substrate that faces the second substrate, the first electrode layer comprising a plurality of first electrode patterns; a second electrode layer disposed on a side of the second substrate that faces the first substrate, the second electrode layer comprising a plurality of second electrode patterns; and a spacer layer disposed between the first substrate and the second substrate and comprising a plurality of holes such that the first electrode patterns are configured to contact the second electrode patterns through the holes.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: September 17, 2019
    Assignee: MedicusTek, Inc.
    Inventors: Chia-Ming Hsu, Chung-Chih Lin, Chi Wen Liu, Chun Lin, Chao-Hung Chou
  • Patent number: 10418290
    Abstract: A method of patterning a semiconductor device includes following steps. First of all, a substrate is provided, and a first target pattern is formed in the substrate. Next, a second target pattern is formed on the substrate, across the first target pattern. Then, a third pattern is formed on a hard mask layer formed on the substrate, by using an electron beam apparatus, wherein two opposite edges of the third pattern are formed under an asymmetry control.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: September 17, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Hon-Huei Liu, Chia-Hung Lin, Yu-Cheng Tung
  • Publication number: 20190244770
    Abstract: A button switch includes a base having a pillar, a cover disposed on the base, a sleeve, an arm adjacent to the pillar and an elastic member having upward-force-applying, extending-rod, and flexible-rod portions. The sleeve jackets the pillar, passes through the cover, and has first and second ribs. The upward-force-applying portion jackets the pillar and abuts against the sleeve and the base to drive the sleeve to move away from the base. The extending-rod portion extends from the upward-force-applying portion to be connected to the flexible-rod portion located under the first rib. When the sleeve is located at a high position, the second rib biases the arm to deform. When the sleeve is located at a low position, the second rib is misaligned with the arm. The flexible-rod portion crosses the first rib to be released and then collides with the cover to make sound as the sleeve is pressed.
    Type: Application
    Filed: January 28, 2019
    Publication date: August 8, 2019
    Inventors: Yu-Chun Hsieh, Yung-Chih Wang, Chen Yang, Chia-Hung Liu, Yen-Hsiao Lin
  • Patent number: 10373779
    Abstract: A key switch includes a base, a key cap, a link bar and a buffer member. A first hook of a first extending arm of the base and a second hook of a second extending arm of the base extend toward opposite directions respectively. An upper linking end of the link bar is movably connected to the key cap. The buffer member is made of material softer than material of the base. When the first hook and the second hook engage with a first engaging portion and a second engaging portion of the buffer member respectively, a recess structure of the buffer member is adjacent to the base to form a restraining structure. A lower linking end of the link bar is movably disposed through the restraining structure. Therefore, the key switch of the present invention has noise reduction capability.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: August 6, 2019
    Assignee: DARFON ELECTRONICS CORP.
    Inventors: Pen-Hui Liao, Chin-Hung Lin, Yen-Hsiao Lin, Hsin-Hung Liu, Chia-Fu Cheng
  • Patent number: 10373579
    Abstract: In an exemplary flat display apparatus and control circuit and method for controlling the flat display apparatus, the flat display apparatus includes a plurality of gate driving units, each of which controls the operation of a scan line in the flat display apparatus. The flat display apparatus provides a first gate high level voltage signal and a second gate high level voltage signal to the gate driving units such that the first and second gate high level voltage signals are used as voltage signals transmitted to corresponding scan lines. The first and second gate high level voltage signals respectively include a falling edge with a slope. Duration time of the falling edge of the first gate high level voltage signal is longer than that of the falling edge of the second gate high level voltage signal.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: August 6, 2019
    Assignee: AU OPTRONICS CORP.
    Inventors: Chun-Fan Chung, Tien-Lun Ting, Chia-Chi Tsai, Ming-Hung Tu, Chien-Huang Liao, Yu-Chieh Chen, Pin-Miao Liu
  • Publication number: 20190236326
    Abstract: A fingerprint sensor includes a die, a plurality of conductive structures, an encapsulant, a plurality of conductive patterns, a first dielectric layer, a second dielectric layer, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The conductive patterns are over the die and are electrically connected to the die and the conductive structures. Top surfaces of the conductive patterns are flat. The first dielectric layer is over the die and the encapsulant. A top surface of the first dielectric layer is coplanar with top surfaces of the conductive patterns. The second dielectric layer covers the first dielectric layer and the conductive patterns. The redistribution structure is over the rear surface of the die.
    Type: Application
    Filed: January 30, 2018
    Publication date: August 1, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ying-Cheng Tseng
  • Publication number: 20190235389
    Abstract: Embodiments of the present disclosure generally provide a digital lithography system that can process both large area substrates as well as semiconductor device substrates, such as wafers. Both the large area substrates and the semiconductor device substrates can be processed in the same system simultaneously. Additionally, the system can accommodate different levels of exposure for forming the features over the substrates. For example, the system can accommodate very precise feature patterning as well as less precise feature patterning. The different exposures can occur in the same chamber simultaneously. Thus, the system is capable of processing both semiconductor device substrates and large area substrates simultaneously while also accommodating very precise feature patterning simultaneous with less precise feature patterning.
    Type: Application
    Filed: December 11, 2018
    Publication date: August 1, 2019
    Inventors: Chien-Hua Lai, Ching-Chang Chen, Shih-Hao Kuo, Tsu-Hui Yang, Hsiu-Jen Wang, Yi-Sheng Liu, Chia-Hung Kao