Patents by Inventor Chia-Jen Chen

Chia-Jen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12228906
    Abstract: A calibration method for machine tools comprises: providing a workpiece on a machine tool; rotating the workpiece around a first rotation axis parallel to a main shaft of the machine tool and processing the workpiece by a first machining mode; measuring a first dimensional error of a shape of the workpiece along directions of first and second linear axes perpendicular to the first rotation axis; calculating a positional error of the first rotation axis according to the first dimensional error; rotating the workpiece around a second rotation axis perpendicular to the main shaft and processing the workpiece by a different second machining mode; measuring a second dimensional error of the shape of the workpiece along a direction of a third linear axis perpendicular to the second rotation axis; calculating a positional error of the second rotation axis according to the second dimensional error.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: February 18, 2025
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chung-Kai Wu, Chin-Ming Chen, Chun-Yu Tsai, Chi-Chen Lin, Chia-Chin Chuang, Ta-Jen Peng
  • Publication number: 20250053821
    Abstract: An auto-regressive method for a large language model includes receiving a hidden state associated with at least one token, generating key data, first value data, and query data according to a received hidden state, generating first positionally encoded key data by encoding the key data positionally, generating positionally encoded query data by encoding the query data positionally, performing first element-wise dot product operations according to the first positionally encoded key data, the positionally encoded query data, and second positionally encoded key data to generate an attention score, performing second element-wise dot product operations according to the first value data, the attention score, and second value data to generate an attention output, and adding the attention output and the hidden state to generate an updated hidden output.
    Type: Application
    Filed: July 11, 2024
    Publication date: February 13, 2025
    Applicant: MediaTek Singapore Pte. Ltd.
    Inventors: Jia Yao Christopher LIM, Kelvin Kae Wen TEH, Po-Yen LIN, Jung Hau FOO, Chia-Wei HSU, Yu-Lung LU, Hung-Jen CHEN, Chung-Li LU, Wai Mun WONG
  • Patent number: 12224179
    Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: February 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Sheng Lin, Chi-Jen Liu, Chi-Hsiang Shen, Te-Ming Kung, Chun-Wei Hsu, Chia-Wei Ho, Yang-Chun Cheng, William Weilun Hong, Liang-Guang Chen, Kei-Wei Chen
  • Publication number: 20250044322
    Abstract: The present invention provides a quick coupling probe card, utilized to test circuit board. The quick coupling probe card comprises a base, a coaxial connector, mechanical connector, and probe holding part, wherein the base has a first surface and a second surface corresponding to the first surface, the coaxial connector arranged on the base has one end above the first surface, and is coupled to the test machine for transmitting the high frequency signal, the mechanical connector is arranged on the first surface for coupling to the test machine, and is closer to a center of the base than the coaxial connector, and the probe holding part, arranged on the second surface and utilized to couple to the coaxial connector, has one end connected to a high frequency probe corresponding to one specific kind of the different kinds of pitches.
    Type: Application
    Filed: May 23, 2024
    Publication date: February 6, 2025
    Inventors: Ya-Hung Lo, Chien-Hsun Chen, Chia-Nan Chou, Shou-Jen Tsai, Fuh-Chyun Tang
  • Patent number: 12218130
    Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chang Hung, Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Yi-Hsuan Hsiao, I-Wei Yang
  • Publication number: 20250019129
    Abstract: A sealing structure includes a box body and a cover body. The box body includes a plurality of side walls respectively including a plurality of outer and inner portions, an annular groove formed on the inner portions, and an annular protrusion portion. Each outer portion has a level difference with the corresponding inner portion. Any two adjacent ones of the side walls form a corner portion. An outer surface of each corner portion forms a sharp corner. The annular groove is arc-shaped at a position corresponding to each corner portion. Each corner portion includes a hollowed-out area. The cover body includes a main body in a polygonal shape with sharp corners, an annular protrusion portion protruding from the main body, and an annular groove. The annular protrusion portions extend into the annular grooves, so that the cover body is sealedly joined to the box body.
    Type: Application
    Filed: July 11, 2024
    Publication date: January 16, 2025
    Applicant: Lite-On Technology Corporation
    Inventors: Yun Hao Fan, Chia Tsang Hsu, Wan-Chen Chen, Ying Hsien Chen, Shuo-Jen Shieh
  • Publication number: 20240429064
    Abstract: Methods for etching metal, such as for processing a metal gate, are provided. A method includes forming a hard mask over the metal, wherein the hard mask includes a sidewall defining an opening; and performing a plasma etching process including cycles of depositing a carbon nitride film on the sidewall and etching the metal.
    Type: Application
    Filed: June 26, 2023
    Publication date: December 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Hsuan CHEN, I-Wei YANG, Chang-Han TSAI, Shu-Uei JANG, Shu-Yuan KU, Yih-Ann LIN, Ryan Chia-Jen CHEN
  • Patent number: 12170332
    Abstract: A semiconductor structure includes a first device and a second device. The first device includes a plurality of first fins, a first work function layer over the plurality of first fins, and a first contact layer over the first work function layer. The second device includes a plurality of second fins, a second work function layer and the first work function layer over the plurality of the second fins, and a second contact layer over the first work function layer and the second work function layer. A distance between a bottom surface of the first work function layer and a bottom surface of the first contact layer is greater than a distance between a side surface of the first work function layer of the first device and a side surface of the first contact layer.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: December 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yuan-Sheng Huang, Ryan Chia-Jen Chen
  • Publication number: 20240385506
    Abstract: In a method of manufacturing a reflective mask, a photo resist layer is formed over a mask blank. The mask blank includes a substrate, a reflective multilayer on the substrate, a capping layer on the reflective multilayer, an absorber layer on the capping layer and a hard mask layer, and the absorber layer is made of Cr, CrO or CrON. The photo resist layer is patterned, the hard mask layer is patterned by using the patterned photo resist layer, the absorber layer is patterned by using the patterned hard mask layer, and an additional element is introduced into the patterned absorber layer to form a converted absorber layer.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chang LEE, Chia-Jen CHEN, Pei-Cheng HSU, Ta-Cheng LIEN
  • Publication number: 20240385111
    Abstract: A mask characterization method comprises measuring an interference signal of a reflection or transmission mask for use in lithography; and determining a quality metric for the reflection or transmission mask based on the interference signal. A mask characterization apparatus comprises a light source arranged to illuminate a reflective or transmissive mask with light whereby mask-reflected or mask-transmitted light is generated; an optical grating arranged to convert the mask-reflected or mask-transmitted light into an interference pattern; and an optical detector array arranged to generate an interference signal by measuring the interference pattern.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Chien-Cheng Chen, Ping-Hsun Lin, Huan-Ling Lee, Ta-Cheng Lien, Chia-Jen Chen, Hsin-Chang Lee
  • Publication number: 20240387528
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first channel region disposed over a substrate, a second channel region disposed adjacent the first channel region, a gate electrode layer disposed in the first and second channel regions, and a first dielectric feature disposed adjacent the gate electrode layer. The first dielectric feature includes a first dielectric material having a first thickness. The structure further includes a second dielectric feature disposed between the first and second channel regions, and the second dielectric feature includes a second dielectric material having a second thickness substantially less than the first thickness. The second thickness ranges from about 1 nm to about 20 nm.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Chen-Huang HUANG, Yu-Ling CHENG, Shun-Hui YANG, An Chyi WEI, Chia-Jen CHEN, Shang-Shuo HUANG, Chia-I LIN, Chih-Chang HUNG
  • Patent number: 12147154
    Abstract: In a method of manufacturing a reflective mask, a photo resist layer is formed over a mask blank. The mask blank includes a substrate, a reflective multilayer on the substrate, a capping layer on the reflective multilayer, an absorber layer on the capping layer and a hard mask layer, and the absorber layer is made of Cr, CrO or CrON. The photo resist layer is patterned, the hard mask layer is patterned by using the patterned photo resist layer, the absorber layer is patterned by using the patterned hard mask layer, and an additional element is introduced into the patterned absorber layer to form a converted absorber layer.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Chang Lee, Chia-Jen Chen, Pei-Cheng Hsu, Ta-Cheng Lien
  • Publication number: 20240379820
    Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Ming-Jhe Sie, Chen-Huang Huang, Shao-Hua Hsu, Cheng-Chung Chang, Szu-Ping Lee, An Chyi Wei, Shiang-Bau Wang, Chia-Jen Chen
  • Publication number: 20240371869
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Publication number: 20240371872
    Abstract: 1. A semiconductor structure includes a first fin; an isolation structure adjacent the first fin; a dielectric layer adjacent the isolation structure; a first oxide layer adjacent the first fin, the isolation structure, and the dielectric layer, and a second oxide layer adjacent the first oxide layer. The first oxide layer and the second oxide layer define a composite oxide layer. A horizontal portion of the composite oxide layer is thicker than a vertical portion of the composite oxide layer.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Sheng Huang, Ryan Chia-Jen Chen
  • Publication number: 20240371704
    Abstract: An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.
    Type: Application
    Filed: July 16, 2024
    Publication date: November 7, 2024
    Inventors: Yi-Chun Chen, Ya-Yi Tsai, I-Wei Yang, Ryan Chia-Jen Chen, Shu-Yuan Ku
  • Publication number: 20240363422
    Abstract: A device includes a semiconductor substrate, and a plurality of semiconductor fins parallel to each other, wherein the plurality of semiconductor fins is a portion of the semiconductor substrate. A Shallow Trench Isolation (STI) region is on a side of the plurality of semiconductor fins. The STI region has a top surface and a non-flat bottom surface, wherein the plurality of semiconductor fins is over the top surface of the STI region.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Chia Tai Lin, Chao-Cheng Chen
  • Publication number: 20240363431
    Abstract: A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Inventors: Chih-Chang Hung, Chieh-Ning Feng, Chun-Liang Lai, Yih-Ann Lin, Ryan Chia-Jen Chen
  • Patent number: 12130548
    Abstract: A reticle is provided. The reticle includes a first reflective multilayer (ML) over a mask substrate and a capping layer over the first reflective ML. The reticle also includes a first absorption layer over the capping layer and a second reflective multilayer (ML) over the first absorption layer. The reticle further includes an etch stop layer over the second reflective ML and a third reflective multilayer (ML) over the etch stop layer. In addition, the reticle includes an absorption film pair over the third reflective ML.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Chang Hsueh, Huan-Ling Lee, Chia-Jen Chen, Hsin-Chang Lee
  • Patent number: 12132050
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen